{ "mode": "man", "parameter": "AS", "section": "1", "url": "https://www.chedong.com/phpMan.php/man/AS/1/json", "generated": "2026-06-09T16:08:04Z", "synopsis": "as [-a[cdghlns][=file]] [--alternate] [-D]\n[--compress-debug-sections] [--nocompress-debug-sections]\n[--debug-prefix-map old=new]\n[--defsym sym=val] [-f] [-g] [--gstabs]\n[--gstabs+] [--gdwarf-] [--gdwarf-sections]\n[--gdwarf-cie-version=VERSION]\n[--help] [-I dir] [-J]\n[-K] [-L] [--listing-lhs-width=NUM]\n[--listing-lhs-width2=NUM] [--listing-rhs-width=NUM]\n[--listing-cont-lines=NUM] [--keep-locals]\n[--no-pad-sections]\n[-o objfile] [-R]\n[--statistics]\n[-v] [-version] [--version]\n[-W] [--warn] [--fatal-warnings] [-w] [-x]\n[-Z] [@FILE]\n[--sectname-subst] [--size-check=[error|warning]]\n[--elf-stt-common=[no|yes]]\n[--generate-missing-build-notes=[no|yes]]\n[--multibyte-handling=[allow|warn|warn-sym-only]]\n[--target-help] [target-options]\n[--|files ...]", "sections": { "NAME": { "content": "AS - the portable GNU assembler.\n", "subsections": [] }, "SYNOPSIS": { "content": "as [-a[cdghlns][=file]] [--alternate] [-D]\n[--compress-debug-sections] [--nocompress-debug-sections]\n[--debug-prefix-map old=new]\n[--defsym sym=val] [-f] [-g] [--gstabs]\n[--gstabs+] [--gdwarf-] [--gdwarf-sections]\n[--gdwarf-cie-version=VERSION]\n[--help] [-I dir] [-J]\n[-K] [-L] [--listing-lhs-width=NUM]\n[--listing-lhs-width2=NUM] [--listing-rhs-width=NUM]\n[--listing-cont-lines=NUM] [--keep-locals]\n[--no-pad-sections]\n[-o objfile] [-R]\n[--statistics]\n[-v] [-version] [--version]\n[-W] [--warn] [--fatal-warnings] [-w] [-x]\n[-Z] [@FILE]\n[--sectname-subst] [--size-check=[error|warning]]\n[--elf-stt-common=[no|yes]]\n[--generate-missing-build-notes=[no|yes]]\n[--multibyte-handling=[allow|warn|warn-sym-only]]\n[--target-help] [target-options]\n[--|files ...]\n", "subsections": [] }, "TARGET": { "content": "Target AArch64 options:\n[-EB|-EL]\n[-mabi=ABI]\n\nTarget Alpha options:\n[-mcpu]\n[-mdebug | -no-mdebug]\n[-replace | -noreplace]\n[-relax] [-g] [-Gsize]\n[-F] [-32addr]\n\nTarget ARC options:\n[-mcpu=cpu]\n[-mA6|-mARC600|-mARC601|-mA7|-mARC700|-mEM|-mHS]\n[-mcode-density]\n[-mrelax]\n[-EB|-EL]\n\nTarget ARM options:\n[-mcpu=processor[+extension...]]\n[-march=architecture[+extension...]]\n[-mfpu=floating-point-format]\n[-mfloat-abi=abi]\n[-meabi=ver]\n[-mthumb]\n[-EB|-EL]\n[-mapcs-32|-mapcs-26|-mapcs-float|\n-mapcs-reentrant]\n[-mthumb-interwork] [-k]\n\nTarget Blackfin options:\n[-mcpu=processor[-sirevision]]\n[-mfdpic]\n[-mno-fdpic]\n[-mnopic]\n\nTarget BPF options:\n[-EL] [-EB]\n\nTarget CRIS options:\n[--underscore | --no-underscore]\n[--pic] [-N]\n[--emulation=criself | --emulation=crisaout]\n[--march=v0v10 | --march=v10 | --march=v32 | --march=commonv10v32]\n\nTarget C-SKY options:\n[-march=arch] [-mcpu=cpu]\n[-EL] [-mlittle-endian] [-EB] [-mbig-endian]\n[-fpic] [-pic]\n[-mljump] [-mno-ljump]\n[-force2bsr] [-mforce2bsr] [-no-force2bsr] [-mno-force2bsr]\n[-jsri2bsr] [-mjsri2bsr] [-no-jsri2bsr ] [-mno-jsri2bsr]\n[-mnolrw ] [-mno-lrw]\n[-melrw] [-mno-elrw]\n[-mlaf ] [-mliterals-after-func]\n[-mno-laf] [-mno-literals-after-func]\n[-mlabr] [-mliterals-after-br]\n[-mno-labr] [-mnoliterals-after-br]\n[-mistack] [-mno-istack]\n[-mhard-float] [-mmp] [-mcp] [-mcache]\n[-msecurity] [-mtrust]\n[-mdsp] [-medsp] [-mvdsp]\n\nTarget D10V options:\n[-O]\n\nTarget D30V options:\n[-O|-n|-N]\n\nTarget EPIPHANY options:\n[-mepiphany|-mepiphany16]\n\nTarget H8/300 options:\n[-h-tick-hex]\n\nTarget i386 options:\n[--32|--x32|--64] [-n]\n[-march=CPU[+EXTENSION...]] [-mtune=CPU]\n\nTarget IA-64 options:\n[-mconstant-gp|-mauto-pic]\n[-milp32|-milp64|-mlp64|-mp64]\n[-mle|mbe]\n[-mtune=itanium1|-mtune=itanium2]\n[-munwind-check=warning|-munwind-check=error]\n[-mhint.b=ok|-mhint.b=warning|-mhint.b=error]\n[-x|-xexplicit] [-xauto] [-xdebug]\n\nTarget IP2K options:\n[-mip2022|-mip2022ext]\n\nTarget M32C options:\n[-m32c|-m16c] [-relax] [-h-tick-hex]\n\nTarget M32R options:\n[--m32rx|--[no-]warn-explicit-parallel-conflicts|\n--W[n]p]\n\nTarget M680X0 options:\n[-l] [-m68000|-m68010|-m68020|...]\n\nTarget M68HC11 options:\n[-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg]\n[-mshort|-mlong]\n[-mshort-double|-mlong-double]\n[--force-long-branches] [--short-branches]\n[--strict-direct-mode] [--print-insn-syntax]\n[--print-opcodes] [--generate-example]\n\nTarget MCORE options:\n[-jsri2bsr] [-sifilter] [-relax]\n[-mcpu=[210|340]]\n\nTarget Meta options:\n[-mcpu=cpu] [-mfpu=cpu] [-mdsp=cpu] Target MICROBLAZE options:\n\nTarget MIPS options:\n[-nocpp] [-EL] [-EB] [-O[optimization level]]\n[-g[debug level]] [-G num] [-KPIC] [-callshared]\n[-nonshared] [-xgot [-mvxworks-pic]\n[-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32]\n[-mfp64] [-mgp64] [-mfpxx]\n[-modd-spreg] [-mno-odd-spreg]\n[-march=CPU] [-mtune=CPU] [-mips1] [-mips2]\n[-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2]\n[-mips32r3] [-mips32r5] [-mips32r6] [-mips64] [-mips64r2]\n[-mips64r3] [-mips64r5] [-mips64r6]\n[-construct-floats] [-no-construct-floats]\n[-mignore-branch-isa] [-mno-ignore-branch-isa]\n[-mnan=encoding]\n[-trap] [-no-break] [-break] [-no-trap]\n[-mips16] [-no-mips16]\n[-mmips16e2] [-mno-mips16e2]\n[-mmicromips] [-mno-micromips]\n[-msmartmips] [-mno-smartmips]\n[-mips3d] [-no-mips3d]\n[-mdmx] [-no-mdmx]\n[-mdsp] [-mno-dsp]\n[-mdspr2] [-mno-dspr2]\n[-mdspr3] [-mno-dspr3]\n[-mmsa] [-mno-msa]\n[-mxpa] [-mno-xpa]\n[-mmt] [-mno-mt]\n[-mmcu] [-mno-mcu]\n[-mcrc] [-mno-crc]\n[-mginv] [-mno-ginv]\n[-mloongson-mmi] [-mno-loongson-mmi]\n[-mloongson-cam] [-mno-loongson-cam]\n[-mloongson-ext] [-mno-loongson-ext]\n[-mloongson-ext2] [-mno-loongson-ext2]\n[-minsn32] [-mno-insn32]\n[-mfix7000] [-mno-fix7000]\n[-mfix-rm7000] [-mno-fix-rm7000]\n[-mfix-vr4120] [-mno-fix-vr4120]\n[-mfix-vr4130] [-mno-fix-vr4130]\n[-mfix-r5900] [-mno-fix-r5900]\n[-mdebug] [-no-mdebug]\n[-mpdr] [-mno-pdr]\n\nTarget MMIX options:\n[--fixed-special-register-names] [--globalize-symbols]\n[--gnu-syntax] [--relax] [--no-predefined-symbols]\n[--no-expand] [--no-merge-gregs] [-x]\n[--linker-allocated-gregs]\n\nTarget Nios II options:\n[-relax-all] [-relax-section] [-no-relax]\n[-EB] [-EL]\n\nTarget NDS32 options:\n[-EL] [-EB] [-O] [-Os] [-mcpu=cpu]\n[-misa=isa] [-mabi=abi] [-mall-ext]\n[-m[no-]16-bit] [-m[no-]perf-ext] [-m[no-]perf2-ext]\n[-m[no-]string-ext] [-m[no-]dsp-ext] [-m[no-]mac] [-m[no-]div]\n[-m[no-]audio-isa-ext] [-m[no-]fpu-sp-ext] [-m[no-]fpu-dp-ext]\n[-m[no-]fpu-fma] [-mfpu-freg=FREG] [-mreduced-regs]\n[-mfull-regs] [-m[no-]dx-regs] [-mpic] [-mno-relax]\n[-mb2bb]\n\nTarget PDP11 options:\n[-mpic|-mno-pic] [-mall] [-mno-extensions]\n[-mextension|-mno-extension]\n[-mcpu] [-mmachine]\n\nTarget picoJava options:\n[-mb|-me]\n\nTarget PowerPC options:\n[-a32|-a64]\n[-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405|\n-m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mgekko|\n-mbroadway|-mppc64|-m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500|\n-me6500|-mppc64bridge|-mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x|\n-mpower6|-mpwr6|-mpower7|-mpwr7|-mpower8|-mpwr8|-mpower9|-mpwr9-ma2|\n-mcell|-mspe|-mspe2|-mtitan|-me300|-mcom]\n[-many] [-maltivec|-mvsx|-mhtm|-mvle]\n[-mregnames|-mno-regnames]\n[-mrelocatable|-mrelocatable-lib|-K PIC] [-memb]\n[-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be]\n[-msolaris|-mno-solaris]\n[-nops=count]\n\nTarget PRU options:\n[-link-relax]\n[-mnolink-relax]\n[-mno-warn-regname-label]\n\nTarget RISC-V options:\n[-fpic|-fPIC|-fno-pic]\n[-march=ISA]\n[-mabi=ABI]\n[-mlittle-endian|-mbig-endian]\n\nTarget RL78 options:\n[-mg10]\n[-m32bit-doubles|-m64bit-doubles]\n\nTarget RX options:\n[-mlittle-endian|-mbig-endian]\n[-m32bit-doubles|-m64bit-doubles]\n[-muse-conventional-section-names]\n[-msmall-data-limit]\n[-mpid]\n[-mrelax]\n[-mint-register=number]\n[-mgcc-abi|-mrx-abi]\n\nTarget s390 options:\n[-m31|-m64] [-mesa|-mzarch] [-march=CPU]\n[-mregnames|-mno-regnames]\n[-mwarn-areg-zero]\n\nTarget SCORE options:\n[-EB][-EL][-FIXDD][-NWARN]\n[-SCORE5][-SCORE5U][-SCORE7][-SCORE3]\n[-march=score7][-march=score3]\n[-USER1][-KPIC][-O0][-G num][-V]\n\nTarget SPARC options:\n[-Av6|-Av7|-Av8|-Aleon|-Asparclet|-Asparclite\n-Av8plus|-Av8plusa|-Av8plusb|-Av8plusc|-Av8plusd\n-Av8plusv|-Av8plusm|-Av9|-Av9a|-Av9b|-Av9c\n-Av9d|-Av9e|-Av9v|-Av9m|-Asparc|-Asparcvis\n-Asparcvis2|-Asparcfmaf|-Asparcima|-Asparcvis3\n-Asparcvisr|-Asparc5]\n[-xarch=v8plus|-xarch=v8plusa]|-xarch=v8plusb|-xarch=v8plusc\n-xarch=v8plusd|-xarch=v8plusv|-xarch=v8plusm|-xarch=v9\n-xarch=v9a|-xarch=v9b|-xarch=v9c|-xarch=v9d|-xarch=v9e\n-xarch=v9v|-xarch=v9m|-xarch=sparc|-xarch=sparcvis\n-xarch=sparcvis2|-xarch=sparcfmaf|-xarch=sparcima\n-xarch=sparcvis3|-xarch=sparcvisr|-xarch=sparc5\n-bump]\n[-32|-64]\n[--enforce-aligned-data][--dcti-couples-detect]\n\nTarget TIC54X options:\n[-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf]\n[-merrors-to-file |-me ]\n\nTarget TIC6X options:\n[-march=arch] [-mbig-endian|-mlittle-endian]\n[-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far]\n[-mpic|-mno-pic]\n\nTarget TILE-Gx options:\n[-m32|-m64][-EB][-EL]\n\nTarget Visium options:\n[-mtune=arch]\n\nTarget Xtensa options:\n[--[no-]text-section-literals] [--[no-]auto-litpools]\n[--[no-]absolute-literals]\n[--[no-]target-align] [--[no-]longcalls]\n[--[no-]transform]\n[--rename-section oldname=newname]\n[--[no-]trampolines]\n[--abi-windowed|--abi-call0]\n\nTarget Z80 options:\n[-march=CPU[-EXT][+EXT]]\n[-local-prefix=PREFIX]\n[-colonless]\n[-sdcc]\n[-fp-s=FORMAT]\n[-fp-d=FORMAT]\n", "subsections": [] }, "DESCRIPTION": { "content": "GNU as is really a family of assemblers. If you use (or have used) the GNU assembler on one\narchitecture, you should find a fairly similar environment when you use it on another\narchitecture. Each version has much in common with the others, including object file\nformats, most assembler directives (often called pseudo-ops) and assembler syntax.\n\nas is primarily intended to assemble the output of the GNU C compiler \"gcc\" for use by the\nlinker \"ld\". Nevertheless, we've tried to make as assemble correctly everything that other\nassemblers for the same machine would assemble. Any exceptions are documented explicitly.\nThis doesn't mean as always uses the same syntax as another assembler for the same\narchitecture; for example, we know of several incompatible versions of 680x0 assembly\nlanguage syntax.\n\nEach time you run as it assembles exactly one source program. The source program is made up\nof one or more files. (The standard input is also a file.)\n\nYou give as a command line that has zero or more input file names. The input files are read\n(from left file name to right). A command-line argument (in any position) that has no\nspecial meaning is taken to be an input file name.\n\nIf you give as no file names it attempts to read one input file from the as standard input,\nwhich is normally your terminal. You may have to type ctl-D to tell as there is no more\nprogram to assemble.\n\nUse -- if you need to explicitly name the standard input file in your command line.\n\nIf the source is empty, as produces a small, empty object file.\n\nas may write warnings and error messages to the standard error file (usually your terminal).\nThis should not happen when a compiler runs as automatically. Warnings report an assumption\nmade so that as could keep assembling a flawed program; errors report a grave problem that\nstops the assembly.\n\nIf you are invoking as via the GNU C compiler, you can use the -Wa option to pass arguments\nthrough to the assembler. The assembler arguments must be separated from each other (and the", "subsections": [ { "name": "-Wa", "content": "gcc -c -g -O -Wa,-alh,-L file.c\n\nThis passes two options to the assembler: -alh (emit a listing to standard output with high-\nlevel and assembly source) and -L (retain local symbols in the symbol table).\n\nUsually you do not need to use this -Wa mechanism, since many compiler command-line options\nare automatically passed to the assembler by the compiler. (You can call the GNU compiler\ndriver with the -v option to see precisely what options it passes to each compilation pass,\nincluding the assembler.)\n" } ] }, "OPTIONS": { "content": "@file\nRead command-line options from file. The options read are inserted in place of the\noriginal @file option. If file does not exist, or cannot be read, then the option will\nbe treated literally, and not removed.\n\nOptions in file are separated by whitespace. A whitespace character may be included in\nan option by surrounding the entire option in either single or double quotes. Any\ncharacter (including a backslash) may be included by prefixing the character to be\nincluded with a backslash. The file may itself contain additional @file options; any\nsuch options will be processed recursively.\n", "subsections": [ { "name": "-a[cdghlmns]", "content": "Turn on listings, in any of a variety of ways:\n\n-ac omit false conditionals\n\n-ad omit debugging directives\n\n-ag include general information, like as version and options passed\n\n-ah include high-level source\n\n-al include assembly\n\n-am include macro expansions\n\n-an omit forms processing\n\n-as include symbols\n\n=file\nset the name of the listing file\n\nYou may combine these options; for example, use -aln for assembly listing without forms\nprocessing. The =file option, if used, must be the last one. By itself, -a defaults to\n-ahls.\n" }, { "name": "--alternate", "content": "Begin in alternate macro mode.\n", "long": "--alternate" }, { "name": "--compress-debug-sections", "content": "Compress DWARF debug sections using zlib with SHFCOMPRESSED from the ELF ABI. The\nresulting object file may not be compatible with older linkers and object file utilities.\nNote if compression would make a given section larger then it is not compressed.\n", "long": "--compress-debug-sections" }, { "name": "--compress-debug-sections=none", "content": "", "long": "--compress-debug-sections", "arg": "none" }, { "name": "--compress-debug-sections=zlib", "content": "", "long": "--compress-debug-sections", "arg": "zlib" }, { "name": "--compress-debug-sections=zlib-gnu", "content": "", "long": "--compress-debug-sections", "arg": "zlib-gnu" }, { "name": "--compress-debug-sections=zlib-gabi", "content": "These options control how DWARF debug sections are compressed.\n--compress-debug-sections=none is equivalent to --nocompress-debug-sections.\n--compress-debug-sections=zlib and --compress-debug-sections=zlib-gabi are equivalent to\n--compress-debug-sections. --compress-debug-sections=zlib-gnu compresses DWARF debug\nsections using zlib. The debug sections are renamed to begin with .zdebug. Note if\ncompression would make a given section larger then it is not compressed nor renamed.\n", "long": "--compress-debug-sections", "arg": "zlib-gabi" }, { "name": "--nocompress-debug-sections", "content": "Do not compress DWARF debug sections. This is usually the default for all targets except\nthe x86/x8664, but a configure time option can be used to override this.\n", "long": "--nocompress-debug-sections" }, { "name": "-D", "content": "assemblers.\n\n--debug-prefix-map old=new\nWhen assembling files in directory old, record debugging information describing them as\nin new instead.\n\n--defsym sym=value\nDefine the symbol sym to be value before assembling the input file. value must be an\ninteger constant. As in C, a leading 0x indicates a hexadecimal value, and a leading 0\nindicates an octal value. The value of the symbol can be overridden inside a source file\nvia the use of a \".set\" pseudo-op.\n", "flag": "-D" }, { "name": "-f", "content": "", "flag": "-f" }, { "name": "-g", "content": "", "flag": "-g" }, { "name": "--gen-debug", "content": "Generate debugging information for each assembler source line using whichever debug\nformat is preferred by the target. This currently means either STABS, ECOFF or DWARF2.\nWhen the debug format is DWARF then a \".debuginfo\" and \".debugline\" section is only\nemitted when the assembly file doesn't generate one itself.\n", "long": "--gen-debug" }, { "name": "--gstabs", "content": "Generate stabs debugging information for each assembler line. This may help debugging\nassembler code, if the debugger can handle it.\n", "long": "--gstabs" }, { "name": "--gstabs+", "content": "Generate stabs debugging information for each assembler line, with GNU extensions that\nprobably only gdb can handle, and that could make other debuggers crash or refuse to read\nyour program. This may help debugging assembler code. Currently the only GNU extension\nis the location of the current working directory at assembling time.\n" }, { "name": "--gdwarf-2", "content": "Generate DWARF2 debugging information for each assembler line. This may help debugging\nassembler code, if the debugger can handle it. Note---this option is only supported by\nsome targets, not all of them.\n", "long": "--gdwarf-2" }, { "name": "--gdwarf-3", "content": "This option is the same as the --gdwarf-2 option, except that it allows for the\npossibility of the generation of extra debug information as per version 3 of the DWARF\nspecification. Note - enabling this option does not guarantee the generation of any\nextra information, the choice to do so is on a per target basis.\n", "long": "--gdwarf-3" }, { "name": "--gdwarf-4", "content": "This option is the same as the --gdwarf-2 option, except that it allows for the\npossibility of the generation of extra debug information as per version 4 of the DWARF\nspecification. Note - enabling this option does not guarantee the generation of any\nextra information, the choice to do so is on a per target basis.\n", "long": "--gdwarf-4" }, { "name": "--gdwarf-5", "content": "This option is the same as the --gdwarf-2 option, except that it allows for the\npossibility of the generation of extra debug information as per version 5 of the DWARF\nspecification. Note - enabling this option does not guarantee the generation of any\nextra information, the choice to do so is on a per target basis.\n", "long": "--gdwarf-5" }, { "name": "--gdwarf-sections", "content": "Instead of creating a .debugline section, create a series of .debugline.foo sections\nwhere foo is the name of the corresponding code section. For example a code section\ncalled .text.func will have its dwarf line number information placed into a section\ncalled .debugline.text.func. If the code section is just called .text then debug line\nsection will still be called just .debugline without any suffix.\n\n--gdwarf-cie-version=version\nControl which version of DWARF Common Information Entries (CIEs) are produced. When this\nflag is not specificed the default is version 1, though some targets can modify this\ndefault. Other possible values for version are 3 or 4.\n", "long": "--gdwarf-sections" }, { "name": "--size-check=error", "content": "", "long": "--size-check", "arg": "error" }, { "name": "--size-check=warning", "content": "Issue an error or warning for invalid ELF .size directive.\n", "long": "--size-check", "arg": "warning" }, { "name": "--elf-stt-common=no", "content": "", "long": "--elf-stt-common", "arg": "no" }, { "name": "--elf-stt-common=yes", "content": "These options control whether the ELF assembler should generate common symbols with the\n\"STTCOMMON\" type. The default can be controlled by a configure option\n--enable-elf-stt-common.\n", "long": "--elf-stt-common", "arg": "yes" }, { "name": "--generate-missing-build-notes=yes", "content": "", "long": "--generate-missing-build-notes", "arg": "yes" }, { "name": "--generate-missing-build-notes=no", "content": "These options control whether the ELF assembler should generate GNU Build attribute notes\nif none are present in the input sources. The default can be controlled by the\n--enable-generate-build-notes configure option.\n", "long": "--generate-missing-build-notes", "arg": "no" }, { "name": "--help", "content": "Print a summary of the command-line options and exit.\n", "long": "--help" }, { "name": "--target-help", "content": "Print a summary of all target specific options and exit.\n", "long": "--target-help" }, { "name": "-I", "content": "Add directory dir to the search list for \".include\" directives.\n", "flag": "-I" }, { "name": "-J", "content": "", "flag": "-J" }, { "name": "-K", "content": "", "flag": "-K" }, { "name": "-L", "content": "", "flag": "-L" }, { "name": "--keep-locals", "content": "Keep (in the symbol table) local symbols. These symbols start with system-specific local\nlabel prefixes, typically .L for ELF systems or L for traditional a.out systems.\n\n--listing-lhs-width=number\nSet the maximum width, in words, of the output data column for an assembler listing to\nnumber.\n\n--listing-lhs-width2=number\nSet the maximum width, in words, of the output data column for continuation lines in an\nassembler listing to number.\n\n--listing-rhs-width=number\nSet the maximum width of an input source line, as displayed in a listing, to number\nbytes.\n\n--listing-cont-lines=number\nSet the maximum number of lines printed in a listing for a single line of input to number\n+ 1.\n", "long": "--keep-locals" }, { "name": "--multibyte-handling=allow", "content": "", "long": "--multibyte-handling", "arg": "allow" }, { "name": "--multibyte-handling=warn", "content": "", "long": "--multibyte-handling", "arg": "warn" }, { "name": "--multibyte-handling=warn-sym-only", "content": "Controls how the assembler handles multibyte characters in the input. The default (which\ncan be restored by using the allow argument) is to allow such characters without\ncomplaint. Using the warn argument will make the assembler generate a warning message\nwhenever any multibyte character is encountered. Using the warn-sym-only argument will\nonly cause a warning to be generated when a symbol is defined with a name that contains\nmultibyte characters. (References to undefined symbols will not generate a warning).\n", "long": "--multibyte-handling", "arg": "warn-sym-only" }, { "name": "--no-pad-sections", "content": "Stop the assembler for padding the ends of output sections to the alignment of that\nsection. The default is to pad the sections, but this can waste space which might be\nneeded on targets which have tight memory constraints.\n", "long": "--no-pad-sections" }, { "name": "-o", "content": "Name the object-file output from as objfile.\n", "flag": "-o" }, { "name": "-R", "content": "", "flag": "-R" }, { "name": "--sectname-subst", "content": "Honor substitution sequences in section names.\n", "long": "--sectname-subst" }, { "name": "--statistics", "content": "Print the maximum space (in bytes) and total time (in seconds) used by assembly.\n", "long": "--statistics" }, { "name": "--strip-local-absolute", "content": "Remove local absolute symbols from the outgoing symbol table.\n", "long": "--strip-local-absolute" }, { "name": "-v", "content": "", "flag": "-v" }, { "name": "-version", "content": "Print the as version.\n" }, { "name": "--version", "content": "Print the as version and exit.\n", "long": "--version" }, { "name": "-W", "content": "", "flag": "-W" }, { "name": "--no-warn", "content": "Suppress warning messages.\n", "long": "--no-warn" }, { "name": "--fatal-warnings", "content": "Treat warnings as errors.\n", "long": "--fatal-warnings" }, { "name": "--warn", "content": "Don't suppress warning messages or treat them as errors.\n", "long": "--warn" }, { "name": "-w", "content": "", "flag": "-w" }, { "name": "-x", "content": "", "flag": "-x" }, { "name": "-Z", "content": "-- | files ...\nStandard input, or source files to assemble.\n\nThe following options are available when as is configured for the 64-bit mode of the ARM\nArchitecture (AArch64).\n", "flag": "-Z" }, { "name": "-EB", "content": "being encoded for a big-endian processor.\n" }, { "name": "-EL", "content": "being encoded for a little-endian processor.\n" }, { "name": "-mabi=", "content": "Specify which ABI the source code uses. The recognized arguments are: \"ilp32\" and\n\"lp64\", which decides the generated object file in ELF32 and ELF64 format respectively.\nThe default is \"lp64\".\n" }, { "name": "-mcpu=", "content": "This option specifies the target processor. The assembler will issue an error message if\nan attempt is made to assemble an instruction which will not execute on the target\nprocessor. The following processor names are recognized: \"cortex-a34\", \"cortex-a35\",\n\"cortex-a53\", \"cortex-a55\", \"cortex-a57\", \"cortex-a65\", \"cortex-a65ae\", \"cortex-a72\",\n\"cortex-a73\", \"cortex-a75\", \"cortex-a76\", \"cortex-a76ae\", \"cortex-a77\", \"cortex-a78\",\n\"cortex-a78ae\", \"cortex-a78c\", \"cortex-a510\", \"cortex-a710\", \"ares\", \"exynos-m1\",\n\"falkor\", \"neoverse-n1\", \"neoverse-n2\", \"neoverse-e1\", \"neoverse-v1\", \"qdf24xx\",\n\"saphira\", \"thunderx\", \"vulcan\", \"xgene1\" \"xgene2\", \"cortex-r82\", \"cortex-x1\", and\n\"cortex-x2\". The special name \"all\" may be used to allow the assembler to accept\ninstructions valid for any supported processor, including all optional extensions.\n\nIn addition to the basic instruction set, the assembler can be told to accept, or\nrestrict, various extension mnemonics that extend the processor.\n\nIf some implementations of a particular processor can have an extension, then then those\nextensions are automatically enabled. Consequently, you will not normally have to\nspecify any additional extensions.\n" }, { "name": "-march=", "content": "This option specifies the target architecture. The assembler will issue an error message\nif an attempt is made to assemble an instruction which will not execute on the target\narchitecture. The following architecture names are recognized: \"armv8-a\", \"armv8.1-a\",\n\"armv8.2-a\", \"armv8.3-a\", \"armv8.4-a\" \"armv8.5-a\", \"armv8.6-a\", \"armv8.7-a\", \"armv8.8-a\",\n\"armv8-r\", \"armv9-a\", \"armv9.1-a\", \"armv9.2-a\", and \"armv9.3-a\".\n\nIf both -mcpu and -march are specified, the assembler will use the setting for -mcpu. If\nneither are specified, the assembler will default to -mcpu=all.\n\nThe architecture option can be extended with the same instruction set extension options\nas the -mcpu option. Unlike -mcpu, extensions are not always enabled by default,\n" }, { "name": "-mverbose-error", "content": "This option enables verbose error messages for AArch64 gas. This option is enabled by\ndefault.\n" }, { "name": "-mno-verbose-error", "content": "This option disables verbose error messages in AArch64 gas.\n\nThe following options are available when as is configured for an Alpha processor.\n" }, { "name": "-m", "content": "This option specifies the target processor. If an attempt is made to assemble an\ninstruction which will not execute on the target processor, the assembler may either\nexpand the instruction as a macro or issue an error message. This option is equivalent\nto the \".arch\" directive.\n\nThe following processor names are recognized: 21064, \"21064a\", 21066, 21068, 21164,\n\"21164a\", \"21164pc\", 21264, \"21264a\", \"21264b\", \"ev4\", \"ev5\", \"lca45\", \"ev5\", \"ev56\",\n\"pca56\", \"ev6\", \"ev67\", \"ev68\". The special name \"all\" may be used to allow the\nassembler to accept instructions valid for any Alpha processor.\n\nIn order to support existing practice in OSF/1 with respect to \".arch\", and existing\npractice within MILO (the Linux ARC bootloader), the numbered processor names (e.g.\n21064) enable the processor-specific PALcode instructions, while the \"electro-vlasic\"\nnames (e.g. \"ev4\") do not.\n", "flag": "-m" }, { "name": "-mdebug", "content": "" }, { "name": "-no-mdebug", "content": "Enables or disables the generation of \".mdebug\" encapsulation for stabs directives and\nprocedure descriptors. The default is to automatically enable \".mdebug\" when the first\nstabs directive is seen.\n" }, { "name": "-relax", "content": "This option forces all relocations to be put into the object file, instead of saving\nspace and resolving some relocations at assembly time. Note that this option does not\npropagate all symbol arithmetic into the object file, because not all symbol arithmetic\ncan be represented. However, the option can still be useful in specific applications.\n" }, { "name": "-replace", "content": "" }, { "name": "-noreplace", "content": "Enables or disables the optimization of procedure calls, both at assemblage and at link\ntime. These options are only available for VMS targets and \"-replace\" is the default.\nSee section 1.4.1 of the OpenVMS Linker Utility Manual.\n" }, { "name": "-g", "content": "mips-tfile to generate debug information for ECOFF, local labels must be passed through\nto the object file. Otherwise this option has no effect.\n", "flag": "-g" }, { "name": "-G", "content": "A local common symbol larger than size is placed in \".bss\", while smaller symbols are\nplaced in \".sbss\".\n", "flag": "-G" }, { "name": "-F", "content": "", "flag": "-F" }, { "name": "-32addr", "content": "These options are ignored for backward compatibility.\n\nThe following options are available when as is configured for an ARC processor.\n" }, { "name": "-mcpu=", "content": "This option selects the core processor variant.\n" }, { "name": "-EB | -EL", "content": "Select either big-endian (-EB) or little-endian (-EL) output.\n" }, { "name": "-mcode-density", "content": "Enable Code Density extension instructions.\n\nThe following options are available when as is configured for the ARM processor family.\n" }, { "name": "-mcpu=", "content": "Specify which ARM processor variant is the target.\n" }, { "name": "-march=", "content": "Specify which ARM architecture variant is used by the target.\n" }, { "name": "-mfpu=", "content": "Select which Floating Point architecture is the target.\n" }, { "name": "-mfloat-abi=", "content": "Select which floating point ABI is in use.\n" }, { "name": "-mthumb", "content": "Enable Thumb only instruction decoding.\n" }, { "name": "-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant", "content": "Select which procedure calling convention is in use.\n" }, { "name": "-EB | -EL", "content": "Select either big-endian (-EB) or little-endian (-EL) output.\n" }, { "name": "-mthumb-interwork", "content": "Specify that the code has been generated with interworking between Thumb and ARM code in\nmind.\n" }, { "name": "-mccs", "content": "Turns on CodeComposer Studio assembly syntax compatibility mode.\n" }, { "name": "-k", "content": "The following options are available when as is configured for the Blackfin processor family.\n", "flag": "-k" }, { "name": "-mcpu= -", "content": "This option specifies the target processor. The optional sirevision is not used in\nassembler. It's here such that GCC can easily pass down its \"-mcpu=\" option. The\nassembler will issue an error message if an attempt is made to assemble an instruction\nwhich will not execute on the target processor. The following processor names are\nrecognized: \"bf504\", \"bf506\", \"bf512\", \"bf514\", \"bf516\", \"bf518\", \"bf522\", \"bf523\",\n\"bf524\", \"bf525\", \"bf526\", \"bf527\", \"bf531\", \"bf532\", \"bf533\", \"bf534\", \"bf535\" (not\nimplemented yet), \"bf536\", \"bf537\", \"bf538\", \"bf539\", \"bf542\", \"bf542m\", \"bf544\",\n\"bf544m\", \"bf547\", \"bf547m\", \"bf548\", \"bf548m\", \"bf549\", \"bf549m\", \"bf561\", and \"bf592\".\n" }, { "name": "-mfdpic", "content": "Assemble for the FDPIC ABI.\n" }, { "name": "-mno-fdpic", "content": "" }, { "name": "-mnopic", "content": "Disable -mfdpic.\n\nThe following options are available when as is configured for the Linux kernel BPF processor\nfamily.\n\n@chapter BPF Dependent Features\n" }, { "name": "Options", "content": "" }, { "name": "-EB", "content": "" }, { "name": "-EL", "content": "Note that if no endianness option is specified in the command line, the host endianness is\nused. See the info pages for documentation of the CRIS-specific options.\n\nThe following options are available when as is configured for the C-SKY processor family.\n" }, { "name": "-march=", "content": "Assemble for architecture archname. The --help option lists valid values for archname.\n" }, { "name": "-mcpu=", "content": "Assemble for architecture cpuname. The --help option lists valid values for cpuname.\n" }, { "name": "-EL", "content": "" }, { "name": "-mlittle-endian", "content": "Generate little-endian output.\n" }, { "name": "-EB", "content": "" }, { "name": "-mbig-endian", "content": "Generate big-endian output.\n" }, { "name": "-fpic", "content": "" }, { "name": "-pic", "content": "Generate position-independent code.\n" }, { "name": "-mljump", "content": "" }, { "name": "-mno-ljump", "content": "Enable/disable transformation of the short branch instructions \"jbf\", \"jbt\", and \"jbr\" to\n\"jmpi\". This option is for V2 processors only. It is ignored on CK801 and CK802\ntargets, which do not support the \"jmpi\" instruction, and is enabled by default for other\nprocessors.\n" }, { "name": "-mbranch-stub", "content": "" }, { "name": "-mno-branch-stub", "content": "Pass through \"RCKCOREPCRELIMM26BY2\" relocations for \"bsr\" instructions to the linker.\n\nThis option is only available for bare-metal C-SKY V2 ELF targets, where it is enabled by\ndefault. It cannot be used in code that will be dynamically linked against shared\nlibraries.\n" }, { "name": "-force2bsr", "content": "" }, { "name": "-mforce2bsr", "content": "" }, { "name": "-no-force2bsr", "content": "" }, { "name": "-mno-force2bsr", "content": "Enable/disable transformation of \"jbsr\" instructions to \"bsr\". This option is always\nenabled (and -mno-force2bsr is ignored) for CK801/CK802 targets. It is also always\nenabled when -mbranch-stub is in effect.\n" }, { "name": "-jsri2bsr", "content": "" }, { "name": "-mjsri2bsr", "content": "" }, { "name": "-no-jsri2bsr", "content": "" }, { "name": "-mno-jsri2bsr", "content": "Enable/disable transformation of \"jsri\" instructions to \"bsr\". This option is enabled by\ndefault.\n" }, { "name": "-mnolrw", "content": "" }, { "name": "-mno-lrw", "content": "Enable/disable transformation of \"lrw\" instructions into a \"movih\"/\"ori\" pair.\n" }, { "name": "-melrw", "content": "" }, { "name": "-mno-elrw", "content": "Enable/disable extended \"lrw\" instructions. This option is enabled by default for\nCK800-series processors.\n" }, { "name": "-mlaf", "content": "" }, { "name": "-mliterals-after-func", "content": "" }, { "name": "-mno-laf", "content": "" }, { "name": "-mno-literals-after-func", "content": "Enable/disable placement of literal pools after each function.\n" }, { "name": "-mlabr", "content": "" }, { "name": "-mliterals-after-br", "content": "" }, { "name": "-mno-labr", "content": "" }, { "name": "-mnoliterals-after-br", "content": "Enable/disable placement of literal pools after unconditional branches. This option is\nenabled by default.\n" }, { "name": "-mistack", "content": "" }, { "name": "-mno-istack", "content": "Enable/disable interrupt stack instructions. This option is enabled by default on CK801,\nCK802, and CK802 processors.\n\nThe following options explicitly enable certain optional instructions. These features are\nalso enabled implicitly by using \"-mcpu=\" to specify a processor that supports it.\n" }, { "name": "-mhard-float", "content": "Enable hard float instructions.\n" }, { "name": "-mmp", "content": "Enable multiprocessor instructions.\n" }, { "name": "-mcp", "content": "Enable coprocessor instructions.\n" }, { "name": "-mcache", "content": "Enable cache prefetch instruction.\n" }, { "name": "-msecurity", "content": "Enable C-SKY security instructions.\n" }, { "name": "-mtrust", "content": "Enable C-SKY trust instructions.\n" }, { "name": "-mdsp", "content": "Enable DSP instructions.\n" }, { "name": "-medsp", "content": "Enable enhanced DSP instructions.\n" }, { "name": "-mvdsp", "content": "Enable vector DSP instructions.\n\nThe following options are available when as is configured for an Epiphany processor.\n" }, { "name": "-mepiphany", "content": "Specifies that the both 32 and 16 bit instructions are allowed. This is the default\nbehavior.\n" }, { "name": "-mepiphany16", "content": "Restricts the permitted instructions to just the 16 bit set.\n\nThe following options are available when as is configured for an H8/300 processor. @chapter\nH8/300 Dependent Features\n" }, { "name": "Options", "content": "The Renesas H8/300 version of \"as\" has one machine-dependent option:\n" }, { "name": "-h-tick-hex", "content": "Support H'00 style hex constants in addition to 0x00 style.\n" }, { "name": "-mach=", "content": "Sets the H8300 machine variant. The following machine names are recognised: \"h8300h\",\n\"h8300hn\", \"h8300s\", \"h8300sn\", \"h8300sx\" and \"h8300sxn\".\n\nThe following options are available when as is configured for an i386 processor.\n" }, { "name": "--32 | --x32 | --64", "content": "Select the word size, either 32 bits or 64 bits. --32 implies Intel i386 architecture,\nwhile --x32 and --64 imply AMD x86-64 architecture with 32-bit or 64-bit word-size\nrespectively.\n\nThese options are only available with the ELF object file format, and require that the\nnecessary BFD support has been included (on a 32-bit platform you have to add\n--enable-64-bit-bfd to configure enable 64-bit usage and use x86-64 as target platform).\n", "long": "--64" }, { "name": "-n", "content": "sections with multi-byte nop instructions such as leal 0(%esi,1),%esi. This switch\ndisables the optimization if a single byte nop (0x90) is explicitly specified as the fill\nbyte for alignment.\n", "flag": "-n" }, { "name": "--divide", "content": "On SVR4-derived platforms, the character / is treated as a comment character, which means\nthat it cannot be used in expressions. The --divide option turns / into a normal\ncharacter. This does not disable / at the beginning of a line starting a comment, or\naffect using # for starting a comment.\n", "long": "--divide" }, { "name": "-march=", "content": "This option specifies the target processor. The assembler will issue an error message if\nan attempt is made to assemble an instruction which will not execute on the target\nprocessor. The following processor names are recognized: \"i8086\", \"i186\", \"i286\",\n\"i386\", \"i486\", \"i586\", \"i686\", \"pentium\", \"pentiumpro\", \"pentiumii\", \"pentiumiii\",\n\"pentium4\", \"prescott\", \"nocona\", \"core\", \"core2\", \"corei7\", \"l1om\", \"k1om\", \"iamcu\",\n\"k6\", \"k62\", \"athlon\", \"opteron\", \"k8\", \"amdfam10\", \"bdver1\", \"bdver2\", \"bdver3\",\n\"bdver4\", \"znver1\", \"znver2\", \"znver3\", \"btver1\", \"btver2\", \"generic32\" and \"generic64\".\n\nIn addition to the basic instruction set, the assembler can be told to accept various\nextension mnemonics. For example, \"-march=i686+sse4+vmx\" extends i686 with sse4 and vmx.\nThe following extensions are currently supported: 8087, 287, 387, 687, \"no87\", \"no287\",\n\"no387\", \"no687\", \"cmov\", \"nocmov\", \"fxsr\", \"nofxsr\", \"mmx\", \"nommx\", \"sse\", \"sse2\",\n\"sse3\", \"sse4a\", \"ssse3\", \"sse4.1\", \"sse4.2\", \"sse4\", \"nosse\", \"nosse2\", \"nosse3\",\n\"nosse4a\", \"nossse3\", \"nosse4.1\", \"nosse4.2\", \"nosse4\", \"avx\", \"avx2\", \"noavx\", \"noavx2\",\n\"adx\", \"rdseed\", \"prfchw\", \"smap\", \"mpx\", \"sha\", \"rdpid\", \"ptwrite\", \"cet\", \"gfni\",\n\"vaes\", \"vpclmulqdq\", \"prefetchwt1\", \"clflushopt\", \"se1\", \"clwb\", \"movdiri\", \"movdir64b\",\n\"enqcmd\", \"serialize\", \"tsxldtrk\", \"kl\", \"nokl\", \"widekl\", \"nowidekl\", \"hreset\",\n\"avx512f\", \"avx512cd\", \"avx512er\", \"avx512pf\", \"avx512vl\", \"avx512bw\", \"avx512dq\",\n\"avx512ifma\", \"avx512vbmi\", \"avx5124fmaps\", \"avx5124vnniw\", \"avx512vpopcntdq\",\n\"avx512vbmi2\", \"avx512vnni\", \"avx512bitalg\", \"avx512vp2intersect\", \"tdx\",\n\"avx512bf16\", \"avxvnni\", \"avx512fp16\", \"noavx512f\", \"noavx512cd\", \"noavx512er\",\n\"noavx512pf\", \"noavx512vl\", \"noavx512bw\", \"noavx512dq\", \"noavx512ifma\", \"noavx512vbmi\",\n\"noavx5124fmaps\", \"noavx5124vnniw\", \"noavx512vpopcntdq\", \"noavx512vbmi2\",\n\"noavx512vnni\", \"noavx512bitalg\", \"noavx512vp2intersect\", \"notdx\", \"noavx512bf16\",\n\"noavxvnni\", \"noavx512fp16\", \"noenqcmd\", \"noserialize\", \"notsxldtrk\", \"amxint8\",\n\"noamxint8\", \"amxbf16\", \"noamxbf16\", \"amxtile\", \"noamxtile\", \"nouintr\", \"nohreset\",\n\"vmx\", \"vmfunc\", \"smx\", \"xsave\", \"xsaveopt\", \"xsavec\", \"xsaves\", \"aes\", \"pclmul\",\n\"fsgsbase\", \"rdrnd\", \"f16c\", \"bmi2\", \"fma\", \"movbe\", \"ept\", \"lzcnt\", \"popcnt\", \"hle\",\n\"rtm\", \"invpcid\", \"clflush\", \"mwaitx\", \"clzero\", \"wbnoinvd\", \"pconfig\", \"waitpkg\",\n\"uintr\", \"cldemote\", \"rdpru\", \"mcommit\", \"seves\", \"lwp\", \"fma4\", \"xop\", \"cx16\",\n\"syscall\", \"rdtscp\", \"3dnow\", \"3dnowa\", \"sse4a\", \"sse5\", \"snp\", \"invlpgb\", \"tlbsync\",\n\"svme\" and \"padlock\". Note that rather than extending a basic instruction set, the\nextension mnemonics starting with \"no\" revoke the respective functionality.\n\nWhen the \".arch\" directive is used with -march, the \".arch\" directive will take\nprecedent.\n" }, { "name": "-mtune=", "content": "This option specifies a processor to optimize for. When used in conjunction with the\n-march option, only instructions of the processor specified by the -march option will be\ngenerated.\n\nValid CPU values are identical to the processor list of -march=CPU.\n" }, { "name": "-msse2avx", "content": "This option specifies that the assembler should encode SSE instructions with VEX prefix.\n" }, { "name": "-muse-unaligned-vector-move", "content": "This option specifies that the assembler should encode aligned vector move as unaligned\nvector move.\n" }, { "name": "-msse-check=", "content": "" }, { "name": "-msse-check=", "content": "" }, { "name": "-msse-check=", "content": "These options control if the assembler should check SSE instructions. -msse-check=none\nwill make the assembler not to check SSE instructions, which is the default.\n-msse-check=warning will make the assembler issue a warning for any SSE instruction.\n-msse-check=error will make the assembler issue an error for any SSE instruction.\n" }, { "name": "-mavxscalar=", "content": "" }, { "name": "-mavxscalar=", "content": "These options control how the assembler should encode scalar AVX instructions.\n-mavxscalar=128 will encode scalar AVX instructions with 128bit vector length, which is\nthe default. -mavxscalar=256 will encode scalar AVX instructions with 256bit vector\nlength.\n\nWARNING: Don't use this for production code - due to CPU errata the resulting code may\nnot work on certain models.\n" }, { "name": "-mvexwig=", "content": "" }, { "name": "-mvexwig=", "content": "These options control how the assembler should encode VEX.W-ignored (WIG) VEX\ninstructions. -mvexwig=0 will encode WIG VEX instructions with vex.w = 0, which is the\ndefault. -mvexwig=1 will encode WIG EVEX instructions with vex.w = 1.\n\nWARNING: Don't use this for production code - due to CPU errata the resulting code may\nnot work on certain models.\n" }, { "name": "-mevexlig=", "content": "" }, { "name": "-mevexlig=", "content": "" }, { "name": "-mevexlig=", "content": "These options control how the assembler should encode length-ignored (LIG) EVEX\ninstructions. -mevexlig=128 will encode LIG EVEX instructions with 128bit vector length,\nwhich is the default. -mevexlig=256 and -mevexlig=512 will encode LIG EVEX instructions\nwith 256bit and 512bit vector length, respectively.\n" }, { "name": "-mevexwig=", "content": "" }, { "name": "-mevexwig=", "content": "These options control how the assembler should encode w-ignored (WIG) EVEX instructions.\n-mevexwig=0 will encode WIG EVEX instructions with evex.w = 0, which is the default.\n-mevexwig=1 will encode WIG EVEX instructions with evex.w = 1.\n" }, { "name": "-mmnemonic=", "content": "" }, { "name": "-mmnemonic=", "content": "This option specifies instruction mnemonic for matching instructions. The\n\".attmnemonic\" and \".intelmnemonic\" directives will take precedent.\n" }, { "name": "-msyntax=", "content": "" }, { "name": "-msyntax=", "content": "This option specifies instruction syntax when processing instructions. The \".attsyntax\"\nand \".intelsyntax\" directives will take precedent.\n" }, { "name": "-mnaked-reg", "content": "This option specifies that registers don't require a % prefix. The \".attsyntax\" and\n\".intelsyntax\" directives will take precedent.\n" }, { "name": "-madd-bnd-prefix", "content": "This option forces the assembler to add BND prefix to all branches, even if such prefix\nwas not explicitly specified in the source code.\n" }, { "name": "-mno-shared", "content": "On ELF target, the assembler normally optimizes out non-PLT relocations against defined\nnon-weak global branch targets with default visibility. The -mshared option tells the\nassembler to generate code which may go into a shared library where all non-weak global\nbranch targets with default visibility can be preempted. The resulting code is slightly\nbigger. This option only affects the handling of branch instructions.\n" }, { "name": "-mbig-obj", "content": "On PE/COFF target this option forces the use of big object file format, which allows more\nthan 32768 sections.\n" }, { "name": "-momit-lock-prefix=", "content": "" }, { "name": "-momit-lock-prefix=", "content": "These options control how the assembler should encode lock prefix. This option is\nintended as a workaround for processors, that fail on lock prefix. This option can only\nbe safely used with single-core, single-thread computers -momit-lock-prefix=yes will omit\nall lock prefixes. -momit-lock-prefix=no will encode lock prefix as usual, which is the\ndefault.\n" }, { "name": "-mfence-as-lock-add=", "content": "" }, { "name": "-mfence-as-lock-add=", "content": "These options control how the assembler should encode lfence, mfence and sfence.\n-mfence-as-lock-add=yes will encode lfence, mfence and sfence as lock addl $0x0, (%rsp)\nin 64-bit mode and lock addl $0x0, (%esp) in 32-bit mode. -mfence-as-lock-add=no will\nencode lfence, mfence and sfence as usual, which is the default.\n" }, { "name": "-mrelax-relocations=", "content": "" }, { "name": "-mrelax-relocations=", "content": "These options control whether the assembler should generate relax relocations,\nR386GOT32X, in 32-bit mode, or RX8664GOTPCRELX and RX8664REXGOTPCRELX, in 64-bit\nmode. -mrelax-relocations=yes will generate relax relocations. -mrelax-relocations=no\nwill not generate relax relocations. The default can be controlled by a configure option\n--enable-x86-relax-relocations.\n" }, { "name": "-malign-branch-boundary=", "content": "This option controls how the assembler should align branches with segment prefixes or\nNOP. NUM must be a power of 2. It should be 0 or no less than 16. Branches will be\naligned within NUM byte boundary. -malign-branch-boundary=0, which is the default,\ndoesn't align branches.\n" }, { "name": "-malign-branch=", "content": "This option specifies types of branches to align. TYPE is combination of jcc, which\naligns conditional jumps, fused, which aligns fused conditional jumps, jmp, which aligns\nunconditional jumps, call which aligns calls, ret, which aligns rets, indirect, which\naligns indirect jumps and calls. The default is -malign-branch=jcc+fused+jmp.\n" }, { "name": "-malign-branch-prefix-size=", "content": "This option specifies the maximum number of prefixes on an instruction to align branches.\nNUM should be between 0 and 5. The default NUM is 5.\n" }, { "name": "-mbranches-within-32B-boundaries", "content": "This option aligns conditional jumps, fused conditional jumps and unconditional jumps\nwithin 32 byte boundary with up to 5 segment prefixes on an instruction. It is\nequivalent to -malign-branch-boundary=32 -malign-branch=jcc+fused+jmp\n-malign-branch-prefix-size=5. The default doesn't align branches.\n" }, { "name": "-mlfence-after-load=", "content": "" }, { "name": "-mlfence-after-load=", "content": "These options control whether the assembler should generate lfence after load\ninstructions. -mlfence-after-load=yes will generate lfence. -mlfence-after-load=no will\nnot generate lfence, which is the default.\n" }, { "name": "-mlfence-before-indirect-branch=", "content": "" }, { "name": "-mlfence-before-indirect-branch=", "content": "" }, { "name": "-mlfence-before-indirect-branch=", "content": "" }, { "name": "-mlfence-before-indirect-branch=", "content": "These options control whether the assembler should generate lfence before indirect near\nbranch instructions. -mlfence-before-indirect-branch=all will generate lfence before\nindirect near branch via register and issue a warning before indirect near branch via\nmemory. It also implicitly sets -mlfence-before-ret=shl when there's no explicit\n-mlfence-before-ret=. -mlfence-before-indirect-branch=register will generate lfence\nbefore indirect near branch via register. -mlfence-before-indirect-branch=memory will\nissue a warning before indirect near branch via memory.\n-mlfence-before-indirect-branch=none will not generate lfence nor issue warning, which is\nthe default. Note that lfence won't be generated before indirect near branch via\nregister with -mlfence-after-load=yes since lfence will be generated after loading branch\ntarget register.\n" }, { "name": "-mlfence-before-ret=", "content": "" }, { "name": "-mlfence-before-ret=", "content": "" }, { "name": "-mlfence-before-ret=", "content": "" }, { "name": "-mlfence-before-ret=", "content": "" }, { "name": "-mlfence-before-ret=", "content": "These options control whether the assembler should generate lfence before ret.\n-mlfence-before-ret=or will generate generate or instruction with lfence.\n-mlfence-before-ret=shl/yes will generate shl instruction with lfence.\n-mlfence-before-ret=not will generate not instruction with lfence.\n-mlfence-before-ret=none will not generate lfence, which is the default.\n" }, { "name": "-mx86-used-note=", "content": "" }, { "name": "-mx86-used-note=", "content": "These options control whether the assembler should generate GNUPROPERTYX86ISA1USED\nand GNUPROPERTYX86FEATURE2USED GNU property notes. The default can be controlled by\nthe --enable-x86-used-note configure option.\n" }, { "name": "-mevexrcig=", "content": "" }, { "name": "-mevexrcig=", "content": "" }, { "name": "-mevexrcig=", "content": "" }, { "name": "-mevexrcig=", "content": "These options control how the assembler should encode SAE-only EVEX instructions.\n-mevexrcig=rne will encode RC bits of EVEX instruction with 00, which is the default.\n-mevexrcig=rd, -mevexrcig=ru and -mevexrcig=rz will encode SAE-only EVEX instructions\nwith 01, 10 and 11 RC bits, respectively.\n" }, { "name": "-mamd64", "content": "" }, { "name": "-mintel64", "content": "This option specifies that the assembler should accept only AMD64 or Intel64 ISA in\n64-bit mode. The default is to accept common, Intel64 only and AMD64 ISAs.\n" }, { "name": "-O0 | -O | -O1 | -O2 | -Os", "content": "Optimize instruction encoding with smaller instruction size. -O and -O1 encode 64-bit\nregister load instructions with 64-bit immediate as 32-bit register load instructions\nwith 31-bit or 32-bits immediates, encode 64-bit register clearing instructions with\n32-bit register clearing instructions, encode 256-bit/512-bit VEX/EVEX vector register\nclearing instructions with 128-bit VEX vector register clearing instructions, encode\n128-bit/256-bit EVEX vector register load/store instructions with VEX vector register\nload/store instructions, and encode 128-bit/256-bit EVEX packed integer logical\ninstructions with 128-bit/256-bit VEX packed integer logical.\n\n-O2 includes -O1 optimization plus encodes 256-bit/512-bit EVEX vector register clearing\ninstructions with 128-bit EVEX vector register clearing instructions. In 64-bit mode VEX\nencoded instructions with commutative source operands will also have their source\noperands swapped if this allows using the 2-byte VEX prefix form instead of the 3-byte\none. Certain forms of AND as well as OR with the same (register) operand specified twice\nwill also be changed to TEST.\n\n-Os includes -O2 optimization plus encodes 16-bit, 32-bit and 64-bit register tests with\nimmediate as 8-bit register test with immediate. -O0 turns off this optimization.\n\nThe following options are available when as is configured for the Ubicom IP2K series.\n", "flag": "-O" }, { "name": "-mip2022ext", "content": "Specifies that the extended IP2022 instructions are allowed.\n" }, { "name": "-mip2022", "content": "Restores the default behaviour, which restricts the permitted instructions to just the\nbasic IP2022 ones.\n\nThe following options are available when as is configured for the Renesas M32C and M16C\nprocessors.\n" }, { "name": "-m32c", "content": "Assemble M32C instructions.\n" }, { "name": "-m16c", "content": "Assemble M16C instructions (the default).\n" }, { "name": "-relax", "content": "Enable support for link-time relaxations.\n" }, { "name": "-h-tick-hex", "content": "Support H'00 style hex constants in addition to 0x00 style.\n\nThe following options are available when as is configured for the Renesas M32R (formerly\nMitsubishi M32R) series.\n" }, { "name": "--m32rx", "content": "Specify which processor in the M32R family is the target. The default is normally the\nM32R, but this option changes it to the M32RX.\n", "long": "--m32rx" }, { "name": "--warn-explicit-parallel-conflicts or --Wp", "content": "Produce warning messages when questionable parallel constructs are encountered.\n", "long": "--Wp" }, { "name": "--no-warn-explicit-parallel-conflicts or --Wnp", "content": "Do not produce warning messages when questionable parallel constructs are encountered.\n\nThe following options are available when as is configured for the Motorola 68000 series.\n", "long": "--Wnp" }, { "name": "-l", "content": "", "flag": "-l" }, { "name": "-m68000 | -m68008 | -m68010 | -m68020 | -m68030", "content": "" }, { "name": "| -m68040 | -m68060 | -m68302 | -m68331 | -m68332", "content": "" }, { "name": "| -m68333 | -m68340 | -mcpu32 | -m5200", "content": "Specify what processor in the 68000 family is the target. The default is normally the\n68020, but this can be changed at configuration time.\n" }, { "name": "-m68881 | -m68882 | -mno-68881 | -mno-68882", "content": "The target machine does (or does not) have a floating-point coprocessor. The default is\nto assume a coprocessor for 68020, 68030, and cpu32. Although the basic 68000 is not\ncompatible with the 68881, a combination of the two can be specified, since it's possible\nto do emulation of the coprocessor instructions with the main processor.\n" }, { "name": "-m68851 | -mno-68851", "content": "The target machine does (or does not) have a memory-management unit coprocessor. The\ndefault is to assume an MMU for 68020 and up.\n\nThe following options are available when as is configured for an Altera Nios II processor.\n" }, { "name": "-relax-section", "content": "Replace identified out-of-range branches with PC-relative \"jmp\" sequences when possible.\nThe generated code sequences are suitable for use in position-independent code, but there\nis a practical limit on the extended branch range because of the length of the sequences.\nThis option is the default.\n" }, { "name": "-relax-all", "content": "Replace branch instructions not determinable to be in range and all call instructions\nwith \"jmp\" and \"callr\" sequences (respectively). This option generates absolute\nrelocations against the target symbols and is not appropriate for position-independent\ncode.\n" }, { "name": "-no-relax", "content": "Do not replace any branches or calls.\n" }, { "name": "-EB", "content": "" }, { "name": "-EL", "content": "" }, { "name": "-march=", "content": "This option specifies the target architecture. The assembler issues an error message if\nan attempt is made to assemble an instruction which will not execute on the target\narchitecture. The following architecture names are recognized: \"r1\", \"r2\". The default\nis \"r1\".\n\nThe following options are available when as is configured for a PRU processor.\n" }, { "name": "-mlink-relax", "content": "Assume that LD would optimize LDI32 instructions by checking the upper 16 bits of the\nexpression. If they are all zeros, then LD would shorten the LDI32 instruction to a\nsingle LDI. In such case \"as\" will output DIFF relocations for diff expressions.\n" }, { "name": "-mno-link-relax", "content": "Assume that LD would not optimize LDI32 instructions. As a consequence, DIFF relocations\nwill not be emitted.\n" }, { "name": "-mno-warn-regname-label", "content": "Do not warn if a label name matches a register name. Usually assembler programmers will\nwant this warning to be emitted. C compilers may want to turn this off.\n\nThe following options are available when as is configured for a MIPS processor.\n" }, { "name": "-G", "content": "This option sets the largest size of an object that can be referenced implicitly with the\n\"gp\" register. It is only accepted for targets that use ECOFF format, such as a\nDECstation running Ultrix. The default value is 8.\n", "flag": "-G" }, { "name": "-EB", "content": "" }, { "name": "-EL", "content": "" }, { "name": "-mips1", "content": "" }, { "name": "-mips2", "content": "" }, { "name": "-mips3", "content": "" }, { "name": "-mips4", "content": "" }, { "name": "-mips5", "content": "" }, { "name": "-mips32", "content": "" }, { "name": "-mips32r2", "content": "" }, { "name": "-mips32r3", "content": "" }, { "name": "-mips32r5", "content": "" }, { "name": "-mips32r6", "content": "" }, { "name": "-mips64", "content": "" }, { "name": "-mips64r2", "content": "" }, { "name": "-mips64r3", "content": "" }, { "name": "-mips64r5", "content": "" }, { "name": "-mips64r6", "content": "Generate code for a particular MIPS Instruction Set Architecture level. -mips1 is an\nalias for -march=r3000, -mips2 is an alias for -march=r6000, -mips3 is an alias for\n-march=r4000 and -mips4 is an alias for -march=r8000. -mips5, -mips32, -mips32r2,\n-mips32r3, -mips32r5, -mips32r6, -mips64, -mips64r2, -mips64r3, -mips64r5, and -mips64r6\ncorrespond to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 Release\n5, MIPS32 Release 6, MIPS64, MIPS64 Release 2, MIPS64 Release 3, MIPS64 Release 5, and\nMIPS64 Release 6 ISA processors, respectively.\n" }, { "name": "-march=", "content": "Generate code for a particular MIPS CPU.\n" }, { "name": "-mtune=", "content": "Schedule and tune for a particular MIPS CPU.\n" }, { "name": "-mfix7000", "content": "" }, { "name": "-mno-fix7000", "content": "Cause nops to be inserted if the read of the destination register of an mfhi or mflo\ninstruction occurs in the following two instructions.\n" }, { "name": "-mfix-rm7000", "content": "" }, { "name": "-mno-fix-rm7000", "content": "Cause nops to be inserted if a dmult or dmultu instruction is followed by a load\ninstruction.\n" }, { "name": "-mfix-r5900", "content": "" }, { "name": "-mno-fix-r5900", "content": "Do not attempt to schedule the preceding instruction into the delay slot of a branch\ninstruction placed at the end of a short loop of six instructions or fewer and always\nschedule a \"nop\" instruction there instead. The short loop bug under certain conditions\ncauses loops to execute only once or twice, due to a hardware bug in the R5900 chip.\n" }, { "name": "-mdebug", "content": "" }, { "name": "-no-mdebug", "content": "Cause stabs-style debugging output to go into an ECOFF-style .mdebug section instead of\nthe standard ELF .stabs sections.\n" }, { "name": "-mpdr", "content": "" }, { "name": "-mno-pdr", "content": "Control generation of \".pdr\" sections.\n" }, { "name": "-mgp32", "content": "" }, { "name": "-mfp32", "content": "The register sizes are normally inferred from the ISA and ABI, but these flags force a\ncertain group of registers to be treated as 32 bits wide at all times. -mgp32 controls\nthe size of general-purpose registers and -mfp32 controls the size of floating-point\nregisters.\n" }, { "name": "-mgp64", "content": "" }, { "name": "-mfp64", "content": "The register sizes are normally inferred from the ISA and ABI, but these flags force a\ncertain group of registers to be treated as 64 bits wide at all times. -mgp64 controls\nthe size of general-purpose registers and -mfp64 controls the size of floating-point\nregisters.\n" }, { "name": "-mfpxx", "content": "The register sizes are normally inferred from the ISA and ABI, but using this flag in\ncombination with -mabi=32 enables an ABI variant which will operate correctly with\nfloating-point registers which are 32 or 64 bits wide.\n" }, { "name": "-modd-spreg", "content": "" }, { "name": "-mno-odd-spreg", "content": "Enable use of floating-point operations on odd-numbered single-precision registers when\nsupported by the ISA. -mfpxx implies -mno-odd-spreg, otherwise the default is\n-modd-spreg.\n" }, { "name": "-mips16", "content": "" }, { "name": "-no-mips16", "content": "Generate code for the MIPS 16 processor. This is equivalent to putting \".module mips16\"\nat the start of the assembly file. -no-mips16 turns off this option.\n" }, { "name": "-mmips16e2", "content": "" }, { "name": "-mno-mips16e2", "content": "Enable the use of MIPS16e2 instructions in MIPS16 mode. This is equivalent to putting\n\".module mips16e2\" at the start of the assembly file. -mno-mips16e2 turns off this\noption.\n" }, { "name": "-mmicromips", "content": "" }, { "name": "-mno-micromips", "content": "Generate code for the microMIPS processor. This is equivalent to putting \".module\nmicromips\" at the start of the assembly file. -mno-micromips turns off this option.\nThis is equivalent to putting \".module nomicromips\" at the start of the assembly file.\n" }, { "name": "-msmartmips", "content": "" }, { "name": "-mno-smartmips", "content": "Enables the SmartMIPS extension to the MIPS32 instruction set. This is equivalent to\nputting \".module smartmips\" at the start of the assembly file. -mno-smartmips turns off\nthis option.\n" }, { "name": "-mips3d", "content": "" }, { "name": "-no-mips3d", "content": "Generate code for the MIPS-3D Application Specific Extension. This tells the assembler\nto accept MIPS-3D instructions. -no-mips3d turns off this option.\n" }, { "name": "-mdmx", "content": "" }, { "name": "-no-mdmx", "content": "Generate code for the MDMX Application Specific Extension. This tells the assembler to\naccept MDMX instructions. -no-mdmx turns off this option.\n" }, { "name": "-mdsp", "content": "" }, { "name": "-mno-dsp", "content": "Generate code for the DSP Release 1 Application Specific Extension. This tells the\nassembler to accept DSP Release 1 instructions. -mno-dsp turns off this option.\n" }, { "name": "-mdspr2", "content": "" }, { "name": "-mno-dspr2", "content": "Generate code for the DSP Release 2 Application Specific Extension. This option implies\n-mdsp. This tells the assembler to accept DSP Release 2 instructions. -mno-dspr2 turns\noff this option.\n" }, { "name": "-mdspr3", "content": "" }, { "name": "-mno-dspr3", "content": "Generate code for the DSP Release 3 Application Specific Extension. This option implies\n-mdsp and -mdspr2. This tells the assembler to accept DSP Release 3 instructions.\n-mno-dspr3 turns off this option.\n" }, { "name": "-mmsa", "content": "" }, { "name": "-mno-msa", "content": "Generate code for the MIPS SIMD Architecture Extension. This tells the assembler to\naccept MSA instructions. -mno-msa turns off this option.\n" }, { "name": "-mxpa", "content": "" }, { "name": "-mno-xpa", "content": "Generate code for the MIPS eXtended Physical Address (XPA) Extension. This tells the\nassembler to accept XPA instructions. -mno-xpa turns off this option.\n" }, { "name": "-mmt", "content": "" }, { "name": "-mno-mt", "content": "Generate code for the MT Application Specific Extension. This tells the assembler to\naccept MT instructions. -mno-mt turns off this option.\n" }, { "name": "-mmcu", "content": "" }, { "name": "-mno-mcu", "content": "Generate code for the MCU Application Specific Extension. This tells the assembler to\naccept MCU instructions. -mno-mcu turns off this option.\n" }, { "name": "-mcrc", "content": "" }, { "name": "-mno-crc", "content": "Generate code for the MIPS cyclic redundancy check (CRC) Application Specific Extension.\nThis tells the assembler to accept CRC instructions. -mno-crc turns off this option.\n" }, { "name": "-mginv", "content": "" }, { "name": "-mno-ginv", "content": "Generate code for the Global INValidate (GINV) Application Specific Extension. This\ntells the assembler to accept GINV instructions. -mno-ginv turns off this option.\n" }, { "name": "-mloongson-mmi", "content": "" }, { "name": "-mno-loongson-mmi", "content": "Generate code for the Loongson MultiMedia extensions Instructions (MMI) Application\nSpecific Extension. This tells the assembler to accept MMI instructions.\n-mno-loongson-mmi turns off this option.\n" }, { "name": "-mloongson-cam", "content": "" }, { "name": "-mno-loongson-cam", "content": "Generate code for the Loongson Content Address Memory (CAM) instructions. This tells the\nassembler to accept Loongson CAM instructions. -mno-loongson-cam turns off this option.\n" }, { "name": "-mloongson-ext", "content": "" }, { "name": "-mno-loongson-ext", "content": "Generate code for the Loongson EXTensions (EXT) instructions. This tells the assembler\nto accept Loongson EXT instructions. -mno-loongson-ext turns off this option.\n" }, { "name": "-mloongson-ext2", "content": "" }, { "name": "-mno-loongson-ext2", "content": "Generate code for the Loongson EXTensions R2 (EXT2) instructions. This option implies\n-mloongson-ext. This tells the assembler to accept Loongson EXT2 instructions.\n-mno-loongson-ext2 turns off this option.\n" }, { "name": "-minsn32", "content": "" }, { "name": "-mno-insn32", "content": "Only use 32-bit instruction encodings when generating code for the microMIPS processor.\nThis option inhibits the use of any 16-bit instructions. This is equivalent to putting\n\".set insn32\" at the start of the assembly file. -mno-insn32 turns off this option.\nThis is equivalent to putting \".set noinsn32\" at the start of the assembly file. By\ndefault -mno-insn32 is selected, allowing all instructions to be used.\n" }, { "name": "--construct-floats", "content": "", "long": "--construct-floats" }, { "name": "--no-construct-floats", "content": "The --no-construct-floats option disables the construction of double width floating point\nconstants by loading the two halves of the value into the two single width floating point\nregisters that make up the double width register. By default --construct-floats is\nselected, allowing construction of these floating point constants.\n", "long": "--no-construct-floats" }, { "name": "--relax-branch", "content": "", "long": "--relax-branch" }, { "name": "--no-relax-branch", "content": "The --relax-branch option enables the relaxation of out-of-range branches. By default\n--no-relax-branch is selected, causing any out-of-range branches to produce an error.\n", "long": "--no-relax-branch" }, { "name": "-mignore-branch-isa", "content": "" }, { "name": "-mno-ignore-branch-isa", "content": "Ignore branch checks for invalid transitions between ISA modes. The semantics of\nbranches does not provide for an ISA mode switch, so in most cases the ISA mode a branch\nhas been encoded for has to be the same as the ISA mode of the branch's target label.\nTherefore GAS has checks implemented that verify in branch assembly that the two ISA\nmodes match. -mignore-branch-isa disables these checks. By default\n-mno-ignore-branch-isa is selected, causing any invalid branch requiring a transition\nbetween ISA modes to produce an error.\n" }, { "name": "-mnan=", "content": "Select between the IEEE 754-2008 (-mnan=2008) or the legacy (-mnan=legacy) NaN encoding\nformat. The latter is the default.\n\n--emulation=name\nThis option was formerly used to switch between ELF and ECOFF output on targets like IRIX\n5 that supported both. MIPS ECOFF support was removed in GAS 2.24, so the option now\nserves little purpose. It is retained for backwards compatibility.\n\nThe available configuration names are: mipself, mipslelf and mipsbelf. Choosing mipself\nnow has no effect, since the output is always ELF. mipslelf and mipsbelf select little-\nand big-endian output respectively, but -EL and -EB are now the preferred options\ninstead.\n" }, { "name": "-nocpp", "content": "as ignores this option. It is accepted for compatibility with the native tools.\n" }, { "name": "--trap", "content": "", "long": "--trap" }, { "name": "--no-trap", "content": "", "long": "--no-trap" }, { "name": "--break", "content": "", "long": "--break" }, { "name": "--no-break", "content": "Control how to deal with multiplication overflow and division by zero. --trap or\n--no-break (which are synonyms) take a trap exception (and only work for Instruction Set\nArchitecture level 2 and higher); --break or --no-trap (also synonyms, and the default)\ntake a break exception.\n", "long": "--no-break" }, { "name": "-n", "content": "instruction from a macro.\n\nThe following options are available when as is configured for a LoongArch processor.\n", "flag": "-n" }, { "name": "-fpic", "content": "" }, { "name": "-fPIC", "content": "Generate position-independent code\n" }, { "name": "-fno-pic", "content": "Don't generate position-independent code (default)\n\nThe following options are available when as is configured for a Meta processor.\n\n\"-mcpu=metac11\"\nGenerate code for Meta 1.1.\n\n\"-mcpu=metac12\"\nGenerate code for Meta 1.2.\n\n\"-mcpu=metac21\"\nGenerate code for Meta 2.1.\n\n\"-mfpu=metac21\"\nAllow code to use FPU hardware of Meta 2.1.\n\nSee the info pages for documentation of the MMIX-specific options.\n\nThe following options are available when as is configured for a NDS32 processor.\n\n\"-O1\"\nOptimize for performance.\n\n\"-Os\"\nOptimize for space.\n\n\"-EL\"\nProduce little endian data output.\n\n\"-EB\"\nProduce little endian data output.\n\n\"-mpic\"\nGenerate PIC.\n\n\"-mno-fp-as-gp-relax\"\nSuppress fp-as-gp relaxation for this file.\n\n\"-mb2bb-relax\"\nBack-to-back branch optimization.\n\n\"-mno-all-relax\"\nSuppress all relaxation for this file.\n\n\"-march=\"\nAssemble for architecture which could be v3, v3j, v3m, v3f, v3s, v2, v2j,\nv2f, v2s.\n\n\"-mbaseline=\"\nAssemble for baseline which could be v2, v3, v3m.\n\n\"-mfpu-freg=FREG\"\nSpecify a FPU configuration.\n\n\"0 8 SP / 4 DP registers\"\n\"1 16 SP / 8 DP registers\"\n\"2 32 SP / 16 DP registers\"\n\"3 32 SP / 32 DP registers\"\n\"-mabi=abi\"\nSpecify a abi version could be v1, v2, v2fp, v2fpp.\n\n\"-m[no-]mac\"\nEnable/Disable Multiply instructions support.\n\n\"-m[no-]div\"\nEnable/Disable Divide instructions support.\n\n\"-m[no-]16bit-ext\"\nEnable/Disable 16-bit extension\n\n\"-m[no-]dx-regs\"\nEnable/Disable d0/d1 registers\n\n\"-m[no-]perf-ext\"\nEnable/Disable Performance extension\n\n\"-m[no-]perf2-ext\"\nEnable/Disable Performance extension 2\n\n\"-m[no-]string-ext\"\nEnable/Disable String extension\n\n\"-m[no-]reduced-regs\"\nEnable/Disable Reduced Register configuration (GPR16) option\n\n\"-m[no-]audio-isa-ext\"\nEnable/Disable AUDIO ISA extension\n\n\"-m[no-]fpu-sp-ext\"\nEnable/Disable FPU SP extension\n\n\"-m[no-]fpu-dp-ext\"\nEnable/Disable FPU DP extension\n\n\"-m[no-]fpu-fma\"\nEnable/Disable FPU fused-multiply-add instructions\n\n\"-mall-ext\"\nTurn on all extensions and instructions support\n\nThe following options are available when as is configured for a PowerPC processor.\n" }, { "name": "-a32", "content": "Generate ELF32 or XCOFF32.\n" }, { "name": "-a64", "content": "Generate ELF64 or XCOFF64.\n" }, { "name": "-K PIC", "content": "Set EFPPCRELOCATABLELIB in ELF flags.\n", "flag": "-K", "arg": "PIC" }, { "name": "-mpwrx | -mpwr2", "content": "Generate code for POWER/2 (RIOS2).\n" }, { "name": "-mpwr", "content": "Generate code for POWER (RIOS1)\n" }, { "name": "-m601", "content": "Generate code for PowerPC 601.\n" }, { "name": "-mppc, -mppc32, -m603, -m604", "content": "Generate code for PowerPC 603/604.\n" }, { "name": "-m403, -m405", "content": "Generate code for PowerPC 403/405.\n" }, { "name": "-m440", "content": "Generate code for PowerPC 440. BookE and some 405 instructions.\n" }, { "name": "-m464", "content": "Generate code for PowerPC 464.\n" }, { "name": "-m476", "content": "Generate code for PowerPC 476.\n" }, { "name": "-m7400, -m7410, -m7450, -m7455", "content": "Generate code for PowerPC 7400/7410/7450/7455.\n" }, { "name": "-m750cl, -mgekko, -mbroadway", "content": "Generate code for PowerPC 750CL/Gekko/Broadway.\n" }, { "name": "-m821, -m850, -m860", "content": "Generate code for PowerPC 821/850/860.\n" }, { "name": "-mppc64, -m620", "content": "Generate code for PowerPC 620/625/630.\n" }, { "name": "-me500, -me500x2", "content": "Generate code for Motorola e500 core complex.\n" }, { "name": "-me500mc", "content": "Generate code for Freescale e500mc core complex.\n" }, { "name": "-me500mc64", "content": "Generate code for Freescale e500mc64 core complex.\n" }, { "name": "-me5500", "content": "Generate code for Freescale e5500 core complex.\n" }, { "name": "-me6500", "content": "Generate code for Freescale e6500 core complex.\n" }, { "name": "-mspe", "content": "Generate code for Motorola SPE instructions.\n" }, { "name": "-mspe2", "content": "Generate code for Freescale SPE2 instructions.\n" }, { "name": "-mtitan", "content": "Generate code for AppliedMicro Titan core complex.\n" }, { "name": "-mppc64bridge", "content": "Generate code for PowerPC 64, including bridge insns.\n" }, { "name": "-mbooke", "content": "Generate code for 32-bit BookE.\n" }, { "name": "-ma2", "content": "Generate code for A2 architecture.\n" }, { "name": "-me300", "content": "Generate code for PowerPC e300 family.\n" }, { "name": "-maltivec", "content": "Generate code for processors with AltiVec instructions.\n" }, { "name": "-mvle", "content": "Generate code for Freescale PowerPC VLE instructions.\n" }, { "name": "-mvsx", "content": "Generate code for processors with Vector-Scalar (VSX) instructions.\n" }, { "name": "-mhtm", "content": "Generate code for processors with Hardware Transactional Memory instructions.\n" }, { "name": "-mpower4, -mpwr4", "content": "Generate code for Power4 architecture.\n" }, { "name": "-mpower5, -mpwr5, -mpwr5x", "content": "Generate code for Power5 architecture.\n" }, { "name": "-mpower6, -mpwr6", "content": "Generate code for Power6 architecture.\n" }, { "name": "-mpower7, -mpwr7", "content": "Generate code for Power7 architecture.\n" }, { "name": "-mpower8, -mpwr8", "content": "Generate code for Power8 architecture.\n" }, { "name": "-mpower9, -mpwr9", "content": "Generate code for Power9 architecture.\n" }, { "name": "-mpower10, -mpwr10", "content": "Generate code for Power10 architecture.\n" }, { "name": "-mcell", "content": "" }, { "name": "-mcell", "content": "Generate code for Cell Broadband Engine architecture.\n" }, { "name": "-mcom", "content": "Generate code Power/PowerPC common instructions.\n" }, { "name": "-many", "content": "Generate code for any architecture (PWR/PWRX/PPC).\n" }, { "name": "-mregnames", "content": "Allow symbolic names for registers.\n" }, { "name": "-mno-regnames", "content": "Do not allow symbolic names for registers.\n" }, { "name": "-mrelocatable", "content": "Support for GCC's -mrelocatable option.\n" }, { "name": "-mrelocatable-lib", "content": "Support for GCC's -mrelocatable-lib option.\n" }, { "name": "-memb", "content": "Set PPCEMB bit in ELF flags.\n" }, { "name": "-mlittle, -mlittle-endian, -le", "content": "Generate code for a little endian machine.\n" }, { "name": "-mbig, -mbig-endian, -be", "content": "Generate code for a big endian machine.\n" }, { "name": "-msolaris", "content": "Generate code for Solaris.\n" }, { "name": "-mno-solaris", "content": "Do not generate code for Solaris.\n" }, { "name": "-nops=", "content": "If an alignment directive inserts more than count nops, put a branch at the beginning to\nskip execution of the nops.\n\nThe following options are available when as is configured for a RISC-V processor.\n" }, { "name": "-fpic", "content": "" }, { "name": "-fPIC", "content": "Generate position-independent code\n" }, { "name": "-fno-pic", "content": "Don't generate position-independent code (default)\n" }, { "name": "-march=ISA", "content": "Select the base isa, as specified by ISA. For example -march=rv32ima. If this option\nand the architecture attributes aren't set, then assembler will check the default\nconfigure setting --with-arch=ISA.\n" }, { "name": "-misa-spec=ISAspec", "content": "Select the default isa spec version. If the version of ISA isn't set by -march, then\nassembler helps to set the version according to the default chosen spec. If this option\nisn't set, then assembler will check the default configure setting\n--with-isa-spec=ISAspec.\n" }, { "name": "-mpriv-spec=PRIVspec", "content": "Select the privileged spec version. We can decide whether the CSR is valid or not\naccording to the chosen spec. If this option and the privilege attributes aren't set,\nthen assembler will check the default configure setting --with-priv-spec=PRIVspec.\n" }, { "name": "-mabi=ABI", "content": "Selects the ABI, which is either \"ilp32\" or \"lp64\", optionally followed by \"f\", \"d\", or\n\"q\" to indicate single-precision, double-precision, or quad-precision floating-point\ncalling convention, or none to indicate the soft-float calling convention. Also, \"ilp32\"\ncan optionally be followed by \"e\" to indicate the RVE ABI, which is always soft-float.\n" }, { "name": "-mrelax", "content": "Take advantage of linker relaxations to reduce the number of instructions required to\nmaterialize symbol addresses. (default)\n" }, { "name": "-mno-relax", "content": "Don't do linker relaxations.\n" }, { "name": "-march-attr", "content": "Generate the default contents for the riscv elf attribute section if the .attribute\ndirectives are not set. This section is used to record the information that a linker or\nruntime loader needs to check compatibility. This information includes ISA string, stack\nalignment requirement, unaligned memory accesses, and the major, minor and revision\nversion of privileged specification.\n" }, { "name": "-mno-arch-attr", "content": "Don't generate the default riscv elf attribute section if the .attribute directives are\nnot set.\n" }, { "name": "-mcsr-check", "content": "Enable the CSR checking for the ISA-dependent CRS and the read-only CSR. The ISA-\ndependent CSR are only valid when the specific ISA is set. The read-only CSR can not be\nwritten by the CSR instructions.\n" }, { "name": "-mno-csr-check", "content": "Don't do CSR checking.\n" }, { "name": "-mlittle-endian", "content": "Generate code for a little endian machine.\n" }, { "name": "-mbig-endian", "content": "Generate code for a big endian machine.\n\nSee the info pages for documentation of the RX-specific options.\n\nThe following options are available when as is configured for the s390 processor family.\n" }, { "name": "-m31", "content": "" }, { "name": "-m64", "content": "Select the word size, either 31/32 bits or 64 bits.\n" }, { "name": "-mesa", "content": "" }, { "name": "-mzarch", "content": "Select the architecture mode, either the Enterprise System Architecture (esa) or the\nz/Architecture mode (zarch).\n" }, { "name": "-march=", "content": "Specify which s390 processor variant is the target, g5 (or arch3), g6, z900 (or arch5),\nz990 (or arch6), z9-109, z9-ec (or arch7), z10 (or arch8), z196 (or arch9), zEC12 (or\narch10), z13 (or arch11), z14 (or arch12), z15 (or arch13), or z16 (or arch14).\n" }, { "name": "-mregnames", "content": "" }, { "name": "-mno-regnames", "content": "Allow or disallow symbolic names for registers.\n" }, { "name": "-mwarn-areg-zero", "content": "Warn whenever the operand for a base or index register has been specified but evaluates\nto zero.\n\nThe following options are available when as is configured for a TMS320C6000 processor.\n" }, { "name": "-march=", "content": "Enable (only) instructions from architecture arch. By default, all instructions are\npermitted.\n\nThe following values of arch are accepted: \"c62x\", \"c64x\", \"c64x+\", \"c67x\", \"c67x+\",\n\"c674x\".\n" }, { "name": "-mdsbt", "content": "" }, { "name": "-mno-dsbt", "content": "The -mdsbt option causes the assembler to generate the \"TagABIDSBT\" attribute with a\nvalue of 1, indicating that the code is using DSBT addressing. The -mno-dsbt option, the\ndefault, causes the tag to have a value of 0, indicating that the code does not use DSBT\naddressing. The linker will emit a warning if objects of different type (DSBT and non-\nDSBT) are linked together.\n" }, { "name": "-mpid=no", "content": "" }, { "name": "-mpid=near", "content": "" }, { "name": "-mpid=far", "content": "The -mpid= option causes the assembler to generate the \"TagABIPID\" attribute with a\nvalue indicating the form of data addressing used by the code. -mpid=no, the default,\nindicates position-dependent data addressing, -mpid=near indicates position-independent\naddressing with GOT accesses using near DP addressing, and -mpid=far indicates position-\nindependent addressing with GOT accesses using far DP addressing. The linker will emit a\nwarning if objects built with different settings of this option are linked together.\n" }, { "name": "-mpic", "content": "" }, { "name": "-mno-pic", "content": "The -mpic option causes the assembler to generate the \"TagABIPIC\" attribute with a\nvalue of 1, indicating that the code is using position-independent code addressing, The\n\"-mno-pic\" option, the default, causes the tag to have a value of 0, indicating position-\ndependent code addressing. The linker will emit a warning if objects of different type\n(position-dependent and position-independent) are linked together.\n" }, { "name": "-mbig-endian", "content": "" }, { "name": "-mlittle-endian", "content": "Generate code for the specified endianness. The default is little-endian.\n\nThe following options are available when as is configured for a TILE-Gx processor.\n" }, { "name": "-m32 | -m64", "content": "Select the word size, either 32 bits or 64 bits.\n" }, { "name": "-EB | -EL", "content": "Select the endianness, either big-endian (-EB) or little-endian (-EL).\n\nThe following option is available when as is configured for a Visium processor.\n" }, { "name": "-mtune=", "content": "This option specifies the target architecture. If an attempt is made to assemble an\ninstruction that will not execute on the target architecture, the assembler will issue an\nerror message.\n\nThe following names are recognized: \"mcm24\" \"mcm\" \"gr5\" \"gr6\"\n\nThe following options are available when as is configured for an Xtensa processor.\n" }, { "name": "--text-section-literals | --no-text-section-literals", "content": "Control the treatment of literal pools. The default is --no-text-section-literals, which\nplaces literals in separate sections in the output file. This allows the literal pool to\nbe placed in a data RAM/ROM. With --text-section-literals, the literals are interspersed\nin the text section in order to keep them as close as possible to their references. This\nmay be necessary for large assembly files, where the literals would otherwise be out of\nrange of the \"L32R\" instructions in the text section. Literals are grouped into pools\nfollowing \".literalposition\" directives or preceding \"ENTRY\" instructions. These\noptions only affect literals referenced via PC-relative \"L32R\" instructions; literals for\nabsolute mode \"L32R\" instructions are handled separately.\n", "long": "--no-text-section-literals" }, { "name": "--auto-litpools | --no-auto-litpools", "content": "Control the treatment of literal pools. The default is --no-auto-litpools, which in the\nabsence of --text-section-literals places literals in separate sections in the output\nfile. This allows the literal pool to be placed in a data RAM/ROM. With\n--auto-litpools, the literals are interspersed in the text section in order to keep them\nas close as possible to their references, explicit \".literalposition\" directives are not\nrequired. This may be necessary for very large functions, where single literal pool at\nthe beginning of the function may not be reachable by \"L32R\" instructions at the end.\nThese options only affect literals referenced via PC-relative \"L32R\" instructions;\nliterals for absolute mode \"L32R\" instructions are handled separately. When used\ntogether with --text-section-literals, --auto-litpools takes precedence.\n", "long": "--no-auto-litpools" }, { "name": "--absolute-literals | --no-absolute-literals", "content": "Indicate to the assembler whether \"L32R\" instructions use absolute or PC-relative\naddressing. If the processor includes the absolute addressing option, the default is to\nuse absolute \"L32R\" relocations. Otherwise, only the PC-relative \"L32R\" relocations can\nbe used.\n", "long": "--no-absolute-literals" }, { "name": "--target-align | --no-target-align", "content": "Enable or disable automatic alignment to reduce branch penalties at some expense in code\nsize. This optimization is enabled by default. Note that the assembler will always\nalign instructions like \"LOOP\" that have fixed alignment requirements.\n", "long": "--no-target-align" }, { "name": "--longcalls | --no-longcalls", "content": "Enable or disable transformation of call instructions to allow calls across a greater\nrange of addresses. This option should be used when call targets can potentially be\nout of range. It may degrade both code size and performance, but the linker can\ngenerally optimize away the unnecessary overhead when a call ends up within range. The\ndefault is --no-longcalls.\n", "long": "--no-longcalls" }, { "name": "--transform | --no-transform", "content": "Enable or disable all assembler transformations of Xtensa instructions, including both\nrelaxation and optimization. The default is --transform; --no-transform should only be\nused in the rare cases when the instructions must be exactly as specified in the assembly\nsource. Using --no-transform causes out of range instruction operands to be errors.\n\n--rename-section oldname=newname\nRename the oldname section to newname. This option can be used multiple times to rename\nmultiple sections.\n", "long": "--no-transform" }, { "name": "--trampolines | --no-trampolines", "content": "Enable or disable transformation of jump instructions to allow jumps across a greater\nrange of addresses. This option should be used when jump targets can potentially be\nout of range. In the absence of such jumps this option does not affect code size or\nperformance. The default is --trampolines.\n", "long": "--no-trampolines" }, { "name": "--abi-windowed | --abi-call0", "content": "Choose ABI tag written to the \".xtensa.info\" section. ABI tag indicates ABI of the\nassembly code. A warning is issued by the linker on an attempt to link object files with\ninconsistent ABI tags. Default ABI is chosen by the Xtensa core configuration.\n\nThe following options are available when as is configured for an Z80 processor.\n\n@chapter Z80 Dependent Features\n", "long": "--abi-call0" }, { "name": "Command-line Options", "content": "" }, { "name": "-march=", "content": "This option specifies the target processor. The assembler will issue an error message if\nan attempt is made to assemble an instruction which will not execute on the target\nprocessor. The following processor names are recognized: \"z80\", \"z180\", \"ez80\", \"gbz80\",\n\"z80n\", \"r800\". In addition to the basic instruction set, the assembler can be told to\naccept some extention mnemonics. For example, \"-march=z180+sli+infc\" extends z180 with\nSLI instructions and IN F,(C). The following extentions are currently supported: \"full\"\n(all known instructions), \"adl\" (ADL CPU mode by default, eZ80 only), \"sli\" (instruction\nknown as SLI, SLL or SL1), \"xyhl\" (instructions with halves of index registers: IXL, IXH,\nIYL, IYH), \"xdcb\" (instructions like RotOp (II+d),R and BitOp n,(II+d),R), \"infc\"\n(instruction IN F,(C) or IN (C)), \"outc0\" (instruction OUT (C),0). Note that rather than\nextending a basic instruction set, the extention mnemonics starting with \"-\" revoke the\nrespective functionality: \"-march=z80-full+xyhl\" first removes all default extentions and\nadds support for index registers halves only.\n\nIf this option is not specified then \"-march=z80+xyhl+infc\" is assumed.\n" }, { "name": "-local-prefix=", "content": "Mark all labels with specified prefix as local. But such label can be marked global\nexplicitly in the code. This option do not change default local label prefix \".L\", it is\njust adds new one.\n" }, { "name": "-colonless", "content": "Accept colonless labels. All symbols at line begin are treated as labels.\n" }, { "name": "-sdcc", "content": "Accept assembler code produced by SDCC.\n" }, { "name": "-fp-s=", "content": "Single precision floating point numbers format. Default: ieee754 (32 bit).\n" }, { "name": "-fp-d=", "content": "Double precision floating point numbers format. Default: ieee754 (64 bit).\n" } ] }, "SEE ALSO": { "content": "gcc(1), ld(1), and the Info entries for binutils and ld.\n", "subsections": [] }, "COPYRIGHT": { "content": "Copyright (c) 1991-2022 Free Software Foundation, Inc.\n\nPermission is granted to copy, distribute and/or modify this document under the terms of the\nGNU Free Documentation License, Version 1.3 or any later version published by the Free\nSoftware Foundation; with no Invariant Sections, with no Front-Cover Texts, and with no Back-\nCover Texts. A copy of the license is included in the section entitled \"GNU Free\nDocumentation License\".\n\n\n\nbinutils-2.38 2025-12-03 AS(1)", "subsections": [] } }, "summary": "AS - the portable GNU assembler.", "flags": [ { "flag": "", "long": null, "arg": null, "description": "Turn on listings, in any of a variety of ways: -ac omit false conditionals -ad omit debugging directives -ag include general information, like as version and options passed -ah include high-level source -al include assembly -am include macro expansions -an omit forms processing -as include symbols =file set the name of the listing file You may combine these options; for example, use -aln for assembly listing without forms processing. The =file option, if used, must be the last one. By itself, -a defaults to -ahls." }, { "flag": "", "long": "--alternate", "arg": null, "description": "Begin in alternate macro mode." }, { "flag": "", "long": "--compress-debug-sections", "arg": null, "description": "Compress DWARF debug sections using zlib with SHFCOMPRESSED from the ELF ABI. The resulting object file may not be compatible with older linkers and object file utilities. Note if compression would make a given section larger then it is not compressed." }, { "flag": "", "long": "--compress-debug-sections", "arg": "none", "description": "" }, { "flag": "", "long": "--compress-debug-sections", "arg": "zlib", "description": "" }, { "flag": "", "long": "--compress-debug-sections", "arg": "zlib-gnu", "description": "" }, { "flag": "", "long": "--compress-debug-sections", "arg": "zlib-gabi", "description": "These options control how DWARF debug sections are compressed. --compress-debug-sections=none is equivalent to --nocompress-debug-sections. --compress-debug-sections=zlib and --compress-debug-sections=zlib-gabi are equivalent to --compress-debug-sections. --compress-debug-sections=zlib-gnu compresses DWARF debug sections using zlib. The debug sections are renamed to begin with .zdebug. Note if compression would make a given section larger then it is not compressed nor renamed." }, { "flag": "", "long": "--nocompress-debug-sections", "arg": null, "description": "Do not compress DWARF debug sections. This is usually the default for all targets except the x86/x8664, but a configure time option can be used to override this." }, { "flag": "-D", "long": null, "arg": null, "description": "assemblers. --debug-prefix-map old=new When assembling files in directory old, record debugging information describing them as in new instead. --defsym sym=value Define the symbol sym to be value before assembling the input file. value must be an integer constant. As in C, a leading 0x indicates a hexadecimal value, and a leading 0 indicates an octal value. The value of the symbol can be overridden inside a source file via the use of a \".set\" pseudo-op." }, { "flag": "-f", "long": null, "arg": null, "description": "" }, { "flag": "-g", "long": null, "arg": null, "description": "" }, { "flag": "", "long": "--gen-debug", "arg": null, "description": "Generate debugging information for each assembler source line using whichever debug format is preferred by the target. This currently means either STABS, ECOFF or DWARF2. When the debug format is DWARF then a \".debuginfo\" and \".debugline\" section is only emitted when the assembly file doesn't generate one itself." }, { "flag": "", "long": "--gstabs", "arg": null, "description": "Generate stabs debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it." }, { "flag": "", "long": null, "arg": null, "description": "Generate stabs debugging information for each assembler line, with GNU extensions that probably only gdb can handle, and that could make other debuggers crash or refuse to read your program. This may help debugging assembler code. Currently the only GNU extension is the location of the current working directory at assembling time." }, { "flag": "", "long": "--gdwarf-2", "arg": null, "description": "Generate DWARF2 debugging information for each assembler line. This may help debugging assembler code, if the debugger can handle it. Note---this option is only supported by some targets, not all of them." }, { "flag": "", "long": "--gdwarf-3", "arg": null, "description": "This option is the same as the --gdwarf-2 option, except that it allows for the possibility of the generation of extra debug information as per version 3 of the DWARF specification. Note - enabling this option does not guarantee the generation of any extra information, the choice to do so is on a per target basis." }, { "flag": "", "long": "--gdwarf-4", "arg": null, "description": "This option is the same as the --gdwarf-2 option, except that it allows for the possibility of the generation of extra debug information as per version 4 of the DWARF specification. Note - enabling this option does not guarantee the generation of any extra information, the choice to do so is on a per target basis." }, { "flag": "", "long": "--gdwarf-5", "arg": null, "description": "This option is the same as the --gdwarf-2 option, except that it allows for the possibility of the generation of extra debug information as per version 5 of the DWARF specification. Note - enabling this option does not guarantee the generation of any extra information, the choice to do so is on a per target basis." }, { "flag": "", "long": "--gdwarf-sections", "arg": null, "description": "Instead of creating a .debugline section, create a series of .debugline.foo sections where foo is the name of the corresponding code section. For example a code section called .text.func will have its dwarf line number information placed into a section called .debugline.text.func. If the code section is just called .text then debug line section will still be called just .debugline without any suffix. --gdwarf-cie-version=version Control which version of DWARF Common Information Entries (CIEs) are produced. When this flag is not specificed the default is version 1, though some targets can modify this default. Other possible values for version are 3 or 4." }, { "flag": "", "long": "--size-check", "arg": "error", "description": "" }, { "flag": "", "long": "--size-check", "arg": "warning", "description": "Issue an error or warning for invalid ELF .size directive." }, { "flag": "", "long": "--elf-stt-common", "arg": "no", "description": "" }, { "flag": "", "long": "--elf-stt-common", "arg": "yes", "description": "These options control whether the ELF assembler should generate common symbols with the \"STTCOMMON\" type. The default can be controlled by a configure option --enable-elf-stt-common." }, { "flag": "", "long": "--generate-missing-build-notes", "arg": "yes", "description": "" }, { "flag": "", "long": "--generate-missing-build-notes", "arg": "no", "description": "These options control whether the ELF assembler should generate GNU Build attribute notes if none are present in the input sources. The default can be controlled by the --enable-generate-build-notes configure option." }, { "flag": "", "long": "--help", "arg": null, "description": "Print a summary of the command-line options and exit." }, { "flag": "", "long": "--target-help", "arg": null, "description": "Print a summary of all target specific options and exit." }, { "flag": "-I", "long": null, "arg": null, "description": "Add directory dir to the search list for \".include\" directives." }, { "flag": "-J", "long": null, "arg": null, "description": "" }, { "flag": "-K", "long": null, "arg": null, "description": "" }, { "flag": "-L", "long": null, "arg": null, "description": "" }, { "flag": "", "long": "--keep-locals", "arg": null, "description": "Keep (in the symbol table) local symbols. These symbols start with system-specific local label prefixes, typically .L for ELF systems or L for traditional a.out systems. --listing-lhs-width=number Set the maximum width, in words, of the output data column for an assembler listing to number. --listing-lhs-width2=number Set the maximum width, in words, of the output data column for continuation lines in an assembler listing to number. --listing-rhs-width=number Set the maximum width of an input source line, as displayed in a listing, to number bytes. --listing-cont-lines=number Set the maximum number of lines printed in a listing for a single line of input to number + 1." }, { "flag": "", "long": "--multibyte-handling", "arg": "allow", "description": "" }, { "flag": "", "long": "--multibyte-handling", "arg": "warn", "description": "" }, { "flag": "", "long": "--multibyte-handling", "arg": "warn-sym-only", "description": "Controls how the assembler handles multibyte characters in the input. The default (which can be restored by using the allow argument) is to allow such characters without complaint. Using the warn argument will make the assembler generate a warning message whenever any multibyte character is encountered. Using the warn-sym-only argument will only cause a warning to be generated when a symbol is defined with a name that contains multibyte characters. (References to undefined symbols will not generate a warning)." }, { "flag": "", "long": "--no-pad-sections", "arg": null, "description": "Stop the assembler for padding the ends of output sections to the alignment of that section. The default is to pad the sections, but this can waste space which might be needed on targets which have tight memory constraints." }, { "flag": "-o", "long": null, "arg": null, "description": "Name the object-file output from as objfile." }, { "flag": "-R", "long": null, "arg": null, "description": "" }, { "flag": "", "long": "--sectname-subst", "arg": null, "description": "Honor substitution sequences in section names." }, { "flag": "", "long": "--statistics", "arg": null, "description": "Print the maximum space (in bytes) and total time (in seconds) used by assembly." }, { "flag": "", "long": "--strip-local-absolute", "arg": null, "description": "Remove local absolute symbols from the outgoing symbol table." }, { "flag": "-v", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Print the as version." }, { "flag": "", "long": "--version", "arg": null, "description": "Print the as version and exit." }, { "flag": "-W", "long": null, "arg": null, "description": "" }, { "flag": "", "long": "--no-warn", "arg": null, "description": "Suppress warning messages." }, { "flag": "", "long": "--fatal-warnings", "arg": null, "description": "Treat warnings as errors." }, { "flag": "", "long": "--warn", "arg": null, "description": "Don't suppress warning messages or treat them as errors." }, { "flag": "-w", "long": null, "arg": null, "description": "" }, { "flag": "-x", "long": null, "arg": null, "description": "" }, { "flag": "-Z", "long": null, "arg": null, "description": "-- | files ... Standard input, or source files to assemble. The following options are available when as is configured for the 64-bit mode of the ARM Architecture (AArch64)." }, { "flag": "", "long": null, "arg": null, "description": "being encoded for a big-endian processor." }, { "flag": "", "long": null, "arg": null, "description": "being encoded for a little-endian processor." }, { "flag": "", "long": null, "arg": null, "description": "Specify which ABI the source code uses. The recognized arguments are: \"ilp32\" and \"lp64\", which decides the generated object file in ELF32 and ELF64 format respectively. The default is \"lp64\"." }, { "flag": "", "long": null, "arg": null, "description": "This option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following processor names are recognized: \"cortex-a34\", \"cortex-a35\", \"cortex-a53\", \"cortex-a55\", \"cortex-a57\", \"cortex-a65\", \"cortex-a65ae\", \"cortex-a72\", \"cortex-a73\", \"cortex-a75\", \"cortex-a76\", \"cortex-a76ae\", \"cortex-a77\", \"cortex-a78\", \"cortex-a78ae\", \"cortex-a78c\", \"cortex-a510\", \"cortex-a710\", \"ares\", \"exynos-m1\", \"falkor\", \"neoverse-n1\", \"neoverse-n2\", \"neoverse-e1\", \"neoverse-v1\", \"qdf24xx\", \"saphira\", \"thunderx\", \"vulcan\", \"xgene1\" \"xgene2\", \"cortex-r82\", \"cortex-x1\", and \"cortex-x2\". The special name \"all\" may be used to allow the assembler to accept instructions valid for any supported processor, including all optional extensions. In addition to the basic instruction set, the assembler can be told to accept, or restrict, various extension mnemonics that extend the processor. If some implementations of a particular processor can have an extension, then then those extensions are automatically enabled. Consequently, you will not normally have to specify any additional extensions." }, { "flag": "", "long": null, "arg": null, "description": "This option specifies the target architecture. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target architecture. The following architecture names are recognized: \"armv8-a\", \"armv8.1-a\", \"armv8.2-a\", \"armv8.3-a\", \"armv8.4-a\" \"armv8.5-a\", \"armv8.6-a\", \"armv8.7-a\", \"armv8.8-a\", \"armv8-r\", \"armv9-a\", \"armv9.1-a\", \"armv9.2-a\", and \"armv9.3-a\". If both -mcpu and -march are specified, the assembler will use the setting for -mcpu. If neither are specified, the assembler will default to -mcpu=all. The architecture option can be extended with the same instruction set extension options as the -mcpu option. Unlike -mcpu, extensions are not always enabled by default," }, { "flag": "", "long": null, "arg": null, "description": "This option enables verbose error messages for AArch64 gas. This option is enabled by default." }, { "flag": "", "long": null, "arg": null, "description": "This option disables verbose error messages in AArch64 gas. The following options are available when as is configured for an Alpha processor." }, { "flag": "-m", "long": null, "arg": null, "description": "This option specifies the target processor. If an attempt is made to assemble an instruction which will not execute on the target processor, the assembler may either expand the instruction as a macro or issue an error message. This option is equivalent to the \".arch\" directive. The following processor names are recognized: 21064, \"21064a\", 21066, 21068, 21164, \"21164a\", \"21164pc\", 21264, \"21264a\", \"21264b\", \"ev4\", \"ev5\", \"lca45\", \"ev5\", \"ev56\", \"pca56\", \"ev6\", \"ev67\", \"ev68\". The special name \"all\" may be used to allow the assembler to accept instructions valid for any Alpha processor. In order to support existing practice in OSF/1 with respect to \".arch\", and existing practice within MILO (the Linux ARC bootloader), the numbered processor names (e.g. 21064) enable the processor-specific PALcode instructions, while the \"electro-vlasic\" names (e.g. \"ev4\") do not." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Enables or disables the generation of \".mdebug\" encapsulation for stabs directives and procedure descriptors. The default is to automatically enable \".mdebug\" when the first stabs directive is seen." }, { "flag": "", "long": null, "arg": null, "description": "This option forces all relocations to be put into the object file, instead of saving space and resolving some relocations at assembly time. Note that this option does not propagate all symbol arithmetic into the object file, because not all symbol arithmetic can be represented. However, the option can still be useful in specific applications." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Enables or disables the optimization of procedure calls, both at assemblage and at link time. These options are only available for VMS targets and \"-replace\" is the default. See section 1.4.1 of the OpenVMS Linker Utility Manual." }, { "flag": "-g", "long": null, "arg": null, "description": "mips-tfile to generate debug information for ECOFF, local labels must be passed through to the object file. Otherwise this option has no effect." }, { "flag": "-G", "long": null, "arg": null, "description": "A local common symbol larger than size is placed in \".bss\", while smaller symbols are placed in \".sbss\"." }, { "flag": "-F", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "These options are ignored for backward compatibility. The following options are available when as is configured for an ARC processor." }, { "flag": "", "long": null, "arg": null, "description": "This option selects the core processor variant." }, { "flag": "", "long": null, "arg": null, "description": "Select either big-endian (-EB) or little-endian (-EL) output." }, { "flag": "", "long": null, "arg": null, "description": "Enable Code Density extension instructions. The following options are available when as is configured for the ARM processor family." }, { "flag": "", "long": null, "arg": null, "description": "Specify which ARM processor variant is the target." }, { "flag": "", "long": null, "arg": null, "description": "Specify which ARM architecture variant is used by the target." }, { "flag": "", "long": null, "arg": null, "description": "Select which Floating Point architecture is the target." }, { "flag": "", "long": null, "arg": null, "description": "Select which floating point ABI is in use." }, { "flag": "", "long": null, "arg": null, "description": "Enable Thumb only instruction decoding." }, { "flag": "", "long": null, "arg": null, "description": "Select which procedure calling convention is in use." }, { "flag": "", "long": null, "arg": null, "description": "Select either big-endian (-EB) or little-endian (-EL) output." }, { "flag": "", "long": null, "arg": null, "description": "Specify that the code has been generated with interworking between Thumb and ARM code in mind." }, { "flag": "", "long": null, "arg": null, "description": "Turns on CodeComposer Studio assembly syntax compatibility mode." }, { "flag": "-k", "long": null, "arg": null, "description": "The following options are available when as is configured for the Blackfin processor family." }, { "flag": "", "long": null, "arg": null, "description": "This option specifies the target processor. The optional sirevision is not used in assembler. It's here such that GCC can easily pass down its \"-mcpu=\" option. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following processor names are recognized: \"bf504\", \"bf506\", \"bf512\", \"bf514\", \"bf516\", \"bf518\", \"bf522\", \"bf523\", \"bf524\", \"bf525\", \"bf526\", \"bf527\", \"bf531\", \"bf532\", \"bf533\", \"bf534\", \"bf535\" (not implemented yet), \"bf536\", \"bf537\", \"bf538\", \"bf539\", \"bf542\", \"bf542m\", \"bf544\", \"bf544m\", \"bf547\", \"bf547m\", \"bf548\", \"bf548m\", \"bf549\", \"bf549m\", \"bf561\", and \"bf592\"." }, { "flag": "", "long": null, "arg": null, "description": "Assemble for the FDPIC ABI." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Disable -mfdpic. The following options are available when as is configured for the Linux kernel BPF processor family. @chapter BPF Dependent Features" }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Note that if no endianness option is specified in the command line, the host endianness is used. See the info pages for documentation of the CRIS-specific options. The following options are available when as is configured for the C-SKY processor family." }, { "flag": "", "long": null, "arg": null, "description": "Assemble for architecture archname. The --help option lists valid values for archname." }, { "flag": "", "long": null, "arg": null, "description": "Assemble for architecture cpuname. The --help option lists valid values for cpuname." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Generate little-endian output." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Generate big-endian output." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Generate position-independent code." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Enable/disable transformation of the short branch instructions \"jbf\", \"jbt\", and \"jbr\" to \"jmpi\". This option is for V2 processors only. It is ignored on CK801 and CK802 targets, which do not support the \"jmpi\" instruction, and is enabled by default for other processors." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Pass through \"RCKCOREPCRELIMM26BY2\" relocations for \"bsr\" instructions to the linker. This option is only available for bare-metal C-SKY V2 ELF targets, where it is enabled by default. It cannot be used in code that will be dynamically linked against shared libraries." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Enable/disable transformation of \"jbsr\" instructions to \"bsr\". This option is always enabled (and -mno-force2bsr is ignored) for CK801/CK802 targets. It is also always enabled when -mbranch-stub is in effect." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Enable/disable transformation of \"jsri\" instructions to \"bsr\". This option is enabled by default." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Enable/disable transformation of \"lrw\" instructions into a \"movih\"/\"ori\" pair." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Enable/disable extended \"lrw\" instructions. This option is enabled by default for CK800-series processors." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Enable/disable placement of literal pools after each function." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Enable/disable placement of literal pools after unconditional branches. This option is enabled by default." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Enable/disable interrupt stack instructions. This option is enabled by default on CK801, CK802, and CK802 processors. The following options explicitly enable certain optional instructions. These features are also enabled implicitly by using \"-mcpu=\" to specify a processor that supports it." }, { "flag": "", "long": null, "arg": null, "description": "Enable hard float instructions." }, { "flag": "", "long": null, "arg": null, "description": "Enable multiprocessor instructions." }, { "flag": "", "long": null, "arg": null, "description": "Enable coprocessor instructions." }, { "flag": "", "long": null, "arg": null, "description": "Enable cache prefetch instruction." }, { "flag": "", "long": null, "arg": null, "description": "Enable C-SKY security instructions." }, { "flag": "", "long": null, "arg": null, "description": "Enable C-SKY trust instructions." }, { "flag": "", "long": null, "arg": null, "description": "Enable DSP instructions." }, { "flag": "", "long": null, "arg": null, "description": "Enable enhanced DSP instructions." }, { "flag": "", "long": null, "arg": null, "description": "Enable vector DSP instructions. The following options are available when as is configured for an Epiphany processor." }, { "flag": "", "long": null, "arg": null, "description": "Specifies that the both 32 and 16 bit instructions are allowed. This is the default behavior." }, { "flag": "", "long": null, "arg": null, "description": "Restricts the permitted instructions to just the 16 bit set. The following options are available when as is configured for an H8/300 processor. @chapter H8/300 Dependent Features" }, { "flag": "", "long": null, "arg": null, "description": "Support H'00 style hex constants in addition to 0x00 style." }, { "flag": "", "long": null, "arg": null, "description": "Sets the H8300 machine variant. The following machine names are recognised: \"h8300h\", \"h8300hn\", \"h8300s\", \"h8300sn\", \"h8300sx\" and \"h8300sxn\". The following options are available when as is configured for an i386 processor." }, { "flag": "", "long": "--64", "arg": null, "description": "Select the word size, either 32 bits or 64 bits. --32 implies Intel i386 architecture, while --x32 and --64 imply AMD x86-64 architecture with 32-bit or 64-bit word-size respectively. These options are only available with the ELF object file format, and require that the necessary BFD support has been included (on a 32-bit platform you have to add --enable-64-bit-bfd to configure enable 64-bit usage and use x86-64 as target platform)." }, { "flag": "-n", "long": null, "arg": null, "description": "sections with multi-byte nop instructions such as leal 0(%esi,1),%esi. This switch disables the optimization if a single byte nop (0x90) is explicitly specified as the fill byte for alignment." }, { "flag": "", "long": "--divide", "arg": null, "description": "On SVR4-derived platforms, the character / is treated as a comment character, which means that it cannot be used in expressions. The --divide option turns / into a normal character. This does not disable / at the beginning of a line starting a comment, or affect using # for starting a comment." }, { "flag": "", "long": null, "arg": null, "description": "This option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following processor names are recognized: \"i8086\", \"i186\", \"i286\", \"i386\", \"i486\", \"i586\", \"i686\", \"pentium\", \"pentiumpro\", \"pentiumii\", \"pentiumiii\", \"pentium4\", \"prescott\", \"nocona\", \"core\", \"core2\", \"corei7\", \"l1om\", \"k1om\", \"iamcu\", \"k6\", \"k62\", \"athlon\", \"opteron\", \"k8\", \"amdfam10\", \"bdver1\", \"bdver2\", \"bdver3\", \"bdver4\", \"znver1\", \"znver2\", \"znver3\", \"btver1\", \"btver2\", \"generic32\" and \"generic64\". In addition to the basic instruction set, the assembler can be told to accept various extension mnemonics. For example, \"-march=i686+sse4+vmx\" extends i686 with sse4 and vmx. The following extensions are currently supported: 8087, 287, 387, 687, \"no87\", \"no287\", \"no387\", \"no687\", \"cmov\", \"nocmov\", \"fxsr\", \"nofxsr\", \"mmx\", \"nommx\", \"sse\", \"sse2\", \"sse3\", \"sse4a\", \"ssse3\", \"sse4.1\", \"sse4.2\", \"sse4\", \"nosse\", \"nosse2\", \"nosse3\", \"nosse4a\", \"nossse3\", \"nosse4.1\", \"nosse4.2\", \"nosse4\", \"avx\", \"avx2\", \"noavx\", \"noavx2\", \"adx\", \"rdseed\", \"prfchw\", \"smap\", \"mpx\", \"sha\", \"rdpid\", \"ptwrite\", \"cet\", \"gfni\", \"vaes\", \"vpclmulqdq\", \"prefetchwt1\", \"clflushopt\", \"se1\", \"clwb\", \"movdiri\", \"movdir64b\", \"enqcmd\", \"serialize\", \"tsxldtrk\", \"kl\", \"nokl\", \"widekl\", \"nowidekl\", \"hreset\", \"avx512f\", \"avx512cd\", \"avx512er\", \"avx512pf\", \"avx512vl\", \"avx512bw\", \"avx512dq\", \"avx512ifma\", \"avx512vbmi\", \"avx5124fmaps\", \"avx5124vnniw\", \"avx512vpopcntdq\", \"avx512vbmi2\", \"avx512vnni\", \"avx512bitalg\", \"avx512vp2intersect\", \"tdx\", \"avx512bf16\", \"avxvnni\", \"avx512fp16\", \"noavx512f\", \"noavx512cd\", \"noavx512er\", \"noavx512pf\", \"noavx512vl\", \"noavx512bw\", \"noavx512dq\", \"noavx512ifma\", \"noavx512vbmi\", \"noavx5124fmaps\", \"noavx5124vnniw\", \"noavx512vpopcntdq\", \"noavx512vbmi2\", \"noavx512vnni\", \"noavx512bitalg\", \"noavx512vp2intersect\", \"notdx\", \"noavx512bf16\", \"noavxvnni\", \"noavx512fp16\", \"noenqcmd\", \"noserialize\", \"notsxldtrk\", \"amxint8\", \"noamxint8\", \"amxbf16\", \"noamxbf16\", \"amxtile\", \"noamxtile\", \"nouintr\", \"nohreset\", \"vmx\", \"vmfunc\", \"smx\", \"xsave\", \"xsaveopt\", \"xsavec\", \"xsaves\", \"aes\", \"pclmul\", \"fsgsbase\", \"rdrnd\", \"f16c\", \"bmi2\", \"fma\", \"movbe\", \"ept\", \"lzcnt\", \"popcnt\", \"hle\", \"rtm\", \"invpcid\", \"clflush\", \"mwaitx\", \"clzero\", \"wbnoinvd\", \"pconfig\", \"waitpkg\", \"uintr\", \"cldemote\", \"rdpru\", \"mcommit\", \"seves\", \"lwp\", \"fma4\", \"xop\", \"cx16\", \"syscall\", \"rdtscp\", \"3dnow\", \"3dnowa\", \"sse4a\", \"sse5\", \"snp\", \"invlpgb\", \"tlbsync\", \"svme\" and \"padlock\". Note that rather than extending a basic instruction set, the extension mnemonics starting with \"no\" revoke the respective functionality. When the \".arch\" directive is used with -march, the \".arch\" directive will take precedent." }, { "flag": "", "long": null, "arg": null, "description": "This option specifies a processor to optimize for. When used in conjunction with the -march option, only instructions of the processor specified by the -march option will be generated. Valid CPU values are identical to the processor list of -march=CPU." }, { "flag": "", "long": null, "arg": null, "description": "This option specifies that the assembler should encode SSE instructions with VEX prefix." }, { "flag": "", "long": null, "arg": null, "description": "This option specifies that the assembler should encode aligned vector move as unaligned vector move." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "These options control if the assembler should check SSE instructions. -msse-check=none will make the assembler not to check SSE instructions, which is the default. -msse-check=warning will make the assembler issue a warning for any SSE instruction. -msse-check=error will make the assembler issue an error for any SSE instruction." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "These options control how the assembler should encode scalar AVX instructions. -mavxscalar=128 will encode scalar AVX instructions with 128bit vector length, which is the default. -mavxscalar=256 will encode scalar AVX instructions with 256bit vector length. WARNING: Don't use this for production code - due to CPU errata the resulting code may not work on certain models." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "These options control how the assembler should encode VEX.W-ignored (WIG) VEX instructions. -mvexwig=0 will encode WIG VEX instructions with vex.w = 0, which is the default. -mvexwig=1 will encode WIG EVEX instructions with vex.w = 1. WARNING: Don't use this for production code - due to CPU errata the resulting code may not work on certain models." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "These options control how the assembler should encode length-ignored (LIG) EVEX instructions. -mevexlig=128 will encode LIG EVEX instructions with 128bit vector length, which is the default. -mevexlig=256 and -mevexlig=512 will encode LIG EVEX instructions with 256bit and 512bit vector length, respectively." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "These options control how the assembler should encode w-ignored (WIG) EVEX instructions. -mevexwig=0 will encode WIG EVEX instructions with evex.w = 0, which is the default. -mevexwig=1 will encode WIG EVEX instructions with evex.w = 1." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "This option specifies instruction mnemonic for matching instructions. The \".attmnemonic\" and \".intelmnemonic\" directives will take precedent." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "This option specifies instruction syntax when processing instructions. The \".attsyntax\" and \".intelsyntax\" directives will take precedent." }, { "flag": "", "long": null, "arg": null, "description": "This option specifies that registers don't require a % prefix. The \".attsyntax\" and \".intelsyntax\" directives will take precedent." }, { "flag": "", "long": null, "arg": null, "description": "This option forces the assembler to add BND prefix to all branches, even if such prefix was not explicitly specified in the source code." }, { "flag": "", "long": null, "arg": null, "description": "On ELF target, the assembler normally optimizes out non-PLT relocations against defined non-weak global branch targets with default visibility. The -mshared option tells the assembler to generate code which may go into a shared library where all non-weak global branch targets with default visibility can be preempted. The resulting code is slightly bigger. This option only affects the handling of branch instructions." }, { "flag": "", "long": null, "arg": null, "description": "On PE/COFF target this option forces the use of big object file format, which allows more than 32768 sections." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "These options control how the assembler should encode lock prefix. This option is intended as a workaround for processors, that fail on lock prefix. This option can only be safely used with single-core, single-thread computers -momit-lock-prefix=yes will omit all lock prefixes. -momit-lock-prefix=no will encode lock prefix as usual, which is the default." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "These options control how the assembler should encode lfence, mfence and sfence. -mfence-as-lock-add=yes will encode lfence, mfence and sfence as lock addl $0x0, (%rsp) in 64-bit mode and lock addl $0x0, (%esp) in 32-bit mode. -mfence-as-lock-add=no will encode lfence, mfence and sfence as usual, which is the default." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "These options control whether the assembler should generate relax relocations, R386GOT32X, in 32-bit mode, or RX8664GOTPCRELX and RX8664REXGOTPCRELX, in 64-bit mode. -mrelax-relocations=yes will generate relax relocations. -mrelax-relocations=no will not generate relax relocations. The default can be controlled by a configure option --enable-x86-relax-relocations." }, { "flag": "", "long": null, "arg": null, "description": "This option controls how the assembler should align branches with segment prefixes or NOP. NUM must be a power of 2. It should be 0 or no less than 16. Branches will be aligned within NUM byte boundary. -malign-branch-boundary=0, which is the default, doesn't align branches." }, { "flag": "", "long": null, "arg": null, "description": "This option specifies types of branches to align. TYPE is combination of jcc, which aligns conditional jumps, fused, which aligns fused conditional jumps, jmp, which aligns unconditional jumps, call which aligns calls, ret, which aligns rets, indirect, which aligns indirect jumps and calls. The default is -malign-branch=jcc+fused+jmp." }, { "flag": "", "long": null, "arg": null, "description": "This option specifies the maximum number of prefixes on an instruction to align branches. NUM should be between 0 and 5. The default NUM is 5." }, { "flag": "", "long": null, "arg": null, "description": "This option aligns conditional jumps, fused conditional jumps and unconditional jumps within 32 byte boundary with up to 5 segment prefixes on an instruction. It is equivalent to -malign-branch-boundary=32 -malign-branch=jcc+fused+jmp -malign-branch-prefix-size=5. The default doesn't align branches." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "These options control whether the assembler should generate lfence after load instructions. -mlfence-after-load=yes will generate lfence. -mlfence-after-load=no will not generate lfence, which is the default." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "These options control whether the assembler should generate lfence before indirect near branch instructions. -mlfence-before-indirect-branch=all will generate lfence before indirect near branch via register and issue a warning before indirect near branch via memory. It also implicitly sets -mlfence-before-ret=shl when there's no explicit -mlfence-before-ret=. -mlfence-before-indirect-branch=register will generate lfence before indirect near branch via register. -mlfence-before-indirect-branch=memory will issue a warning before indirect near branch via memory. -mlfence-before-indirect-branch=none will not generate lfence nor issue warning, which is the default. Note that lfence won't be generated before indirect near branch via register with -mlfence-after-load=yes since lfence will be generated after loading branch target register." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "These options control whether the assembler should generate lfence before ret. -mlfence-before-ret=or will generate generate or instruction with lfence. -mlfence-before-ret=shl/yes will generate shl instruction with lfence. -mlfence-before-ret=not will generate not instruction with lfence. -mlfence-before-ret=none will not generate lfence, which is the default." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "These options control whether the assembler should generate GNUPROPERTYX86ISA1USED and GNUPROPERTYX86FEATURE2USED GNU property notes. The default can be controlled by the --enable-x86-used-note configure option." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "These options control how the assembler should encode SAE-only EVEX instructions. -mevexrcig=rne will encode RC bits of EVEX instruction with 00, which is the default. -mevexrcig=rd, -mevexrcig=ru and -mevexrcig=rz will encode SAE-only EVEX instructions with 01, 10 and 11 RC bits, respectively." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "This option specifies that the assembler should accept only AMD64 or Intel64 ISA in 64-bit mode. The default is to accept common, Intel64 only and AMD64 ISAs." }, { "flag": "-O", "long": null, "arg": null, "description": "Optimize instruction encoding with smaller instruction size. -O and -O1 encode 64-bit register load instructions with 64-bit immediate as 32-bit register load instructions with 31-bit or 32-bits immediates, encode 64-bit register clearing instructions with 32-bit register clearing instructions, encode 256-bit/512-bit VEX/EVEX vector register clearing instructions with 128-bit VEX vector register clearing instructions, encode 128-bit/256-bit EVEX vector register load/store instructions with VEX vector register load/store instructions, and encode 128-bit/256-bit EVEX packed integer logical instructions with 128-bit/256-bit VEX packed integer logical. -O2 includes -O1 optimization plus encodes 256-bit/512-bit EVEX vector register clearing instructions with 128-bit EVEX vector register clearing instructions. In 64-bit mode VEX encoded instructions with commutative source operands will also have their source operands swapped if this allows using the 2-byte VEX prefix form instead of the 3-byte one. Certain forms of AND as well as OR with the same (register) operand specified twice will also be changed to TEST. -Os includes -O2 optimization plus encodes 16-bit, 32-bit and 64-bit register tests with immediate as 8-bit register test with immediate. -O0 turns off this optimization. The following options are available when as is configured for the Ubicom IP2K series." }, { "flag": "", "long": null, "arg": null, "description": "Specifies that the extended IP2022 instructions are allowed." }, { "flag": "", "long": null, "arg": null, "description": "Restores the default behaviour, which restricts the permitted instructions to just the basic IP2022 ones. The following options are available when as is configured for the Renesas M32C and M16C processors." }, { "flag": "", "long": null, "arg": null, "description": "Assemble M32C instructions." }, { "flag": "", "long": null, "arg": null, "description": "Assemble M16C instructions (the default)." }, { "flag": "", "long": null, "arg": null, "description": "Enable support for link-time relaxations." }, { "flag": "", "long": null, "arg": null, "description": "Support H'00 style hex constants in addition to 0x00 style. The following options are available when as is configured for the Renesas M32R (formerly Mitsubishi M32R) series." }, { "flag": "", "long": "--m32rx", "arg": null, "description": "Specify which processor in the M32R family is the target. The default is normally the M32R, but this option changes it to the M32RX." }, { "flag": "", "long": "--Wp", "arg": null, "description": "Produce warning messages when questionable parallel constructs are encountered." }, { "flag": "", "long": "--Wnp", "arg": null, "description": "Do not produce warning messages when questionable parallel constructs are encountered. The following options are available when as is configured for the Motorola 68000 series." }, { "flag": "-l", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "The target machine does (or does not) have a floating-point coprocessor. The default is to assume a coprocessor for 68020, 68030, and cpu32. Although the basic 68000 is not compatible with the 68881, a combination of the two can be specified, since it's possible to do emulation of the coprocessor instructions with the main processor." }, { "flag": "", "long": null, "arg": null, "description": "The target machine does (or does not) have a memory-management unit coprocessor. The default is to assume an MMU for 68020 and up. The following options are available when as is configured for an Altera Nios II processor." }, { "flag": "", "long": null, "arg": null, "description": "Replace identified out-of-range branches with PC-relative \"jmp\" sequences when possible. The generated code sequences are suitable for use in position-independent code, but there is a practical limit on the extended branch range because of the length of the sequences. This option is the default." }, { "flag": "", "long": null, "arg": null, "description": "Replace branch instructions not determinable to be in range and all call instructions with \"jmp\" and \"callr\" sequences (respectively). This option generates absolute relocations against the target symbols and is not appropriate for position-independent code." }, { "flag": "", "long": null, "arg": null, "description": "Do not replace any branches or calls." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "This option specifies the target architecture. The assembler issues an error message if an attempt is made to assemble an instruction which will not execute on the target architecture. The following architecture names are recognized: \"r1\", \"r2\". The default is \"r1\". The following options are available when as is configured for a PRU processor." }, { "flag": "", "long": null, "arg": null, "description": "Assume that LD would optimize LDI32 instructions by checking the upper 16 bits of the expression. If they are all zeros, then LD would shorten the LDI32 instruction to a single LDI. In such case \"as\" will output DIFF relocations for diff expressions." }, { "flag": "", "long": null, "arg": null, "description": "Assume that LD would not optimize LDI32 instructions. As a consequence, DIFF relocations will not be emitted." }, { "flag": "", "long": null, "arg": null, "description": "Do not warn if a label name matches a register name. Usually assembler programmers will want this warning to be emitted. C compilers may want to turn this off. The following options are available when as is configured for a MIPS processor." }, { "flag": "-G", "long": null, "arg": null, "description": "This option sets the largest size of an object that can be referenced implicitly with the \"gp\" register. It is only accepted for targets that use ECOFF format, such as a DECstation running Ultrix. The default value is 8." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Generate code for a particular MIPS Instruction Set Architecture level. -mips1 is an alias for -march=r3000, -mips2 is an alias for -march=r6000, -mips3 is an alias for -march=r4000 and -mips4 is an alias for -march=r8000. -mips5, -mips32, -mips32r2, -mips32r3, -mips32r5, -mips32r6, -mips64, -mips64r2, -mips64r3, -mips64r5, and -mips64r6 correspond to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32 Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64, MIPS64 Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64 Release 6 ISA processors, respectively." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for a particular MIPS CPU." }, { "flag": "", "long": null, "arg": null, "description": "Schedule and tune for a particular MIPS CPU." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Cause nops to be inserted if the read of the destination register of an mfhi or mflo instruction occurs in the following two instructions." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Cause nops to be inserted if a dmult or dmultu instruction is followed by a load instruction." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Do not attempt to schedule the preceding instruction into the delay slot of a branch instruction placed at the end of a short loop of six instructions or fewer and always schedule a \"nop\" instruction there instead. The short loop bug under certain conditions causes loops to execute only once or twice, due to a hardware bug in the R5900 chip." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Cause stabs-style debugging output to go into an ECOFF-style .mdebug section instead of the standard ELF .stabs sections." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Control generation of \".pdr\" sections." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "The register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 32 bits wide at all times. -mgp32 controls the size of general-purpose registers and -mfp32 controls the size of floating-point registers." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "The register sizes are normally inferred from the ISA and ABI, but these flags force a certain group of registers to be treated as 64 bits wide at all times. -mgp64 controls the size of general-purpose registers and -mfp64 controls the size of floating-point registers." }, { "flag": "", "long": null, "arg": null, "description": "The register sizes are normally inferred from the ISA and ABI, but using this flag in combination with -mabi=32 enables an ABI variant which will operate correctly with floating-point registers which are 32 or 64 bits wide." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Enable use of floating-point operations on odd-numbered single-precision registers when supported by the ISA. -mfpxx implies -mno-odd-spreg, otherwise the default is -modd-spreg." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Generate code for the MIPS 16 processor. This is equivalent to putting \".module mips16\" at the start of the assembly file. -no-mips16 turns off this option." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Enable the use of MIPS16e2 instructions in MIPS16 mode. This is equivalent to putting \".module mips16e2\" at the start of the assembly file. -mno-mips16e2 turns off this option." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Generate code for the microMIPS processor. This is equivalent to putting \".module micromips\" at the start of the assembly file. -mno-micromips turns off this option. This is equivalent to putting \".module nomicromips\" at the start of the assembly file." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Enables the SmartMIPS extension to the MIPS32 instruction set. This is equivalent to putting \".module smartmips\" at the start of the assembly file. -mno-smartmips turns off this option." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Generate code for the MIPS-3D Application Specific Extension. This tells the assembler to accept MIPS-3D instructions. -no-mips3d turns off this option." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Generate code for the MDMX Application Specific Extension. This tells the assembler to accept MDMX instructions. -no-mdmx turns off this option." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Generate code for the DSP Release 1 Application Specific Extension. This tells the assembler to accept DSP Release 1 instructions. -mno-dsp turns off this option." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Generate code for the DSP Release 2 Application Specific Extension. This option implies -mdsp. This tells the assembler to accept DSP Release 2 instructions. -mno-dspr2 turns off this option." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Generate code for the DSP Release 3 Application Specific Extension. This option implies -mdsp and -mdspr2. This tells the assembler to accept DSP Release 3 instructions. -mno-dspr3 turns off this option." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Generate code for the MIPS SIMD Architecture Extension. This tells the assembler to accept MSA instructions. -mno-msa turns off this option." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Generate code for the MIPS eXtended Physical Address (XPA) Extension. This tells the assembler to accept XPA instructions. -mno-xpa turns off this option." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Generate code for the MT Application Specific Extension. This tells the assembler to accept MT instructions. -mno-mt turns off this option." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Generate code for the MCU Application Specific Extension. This tells the assembler to accept MCU instructions. -mno-mcu turns off this option." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Generate code for the MIPS cyclic redundancy check (CRC) Application Specific Extension. This tells the assembler to accept CRC instructions. -mno-crc turns off this option." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Generate code for the Global INValidate (GINV) Application Specific Extension. This tells the assembler to accept GINV instructions. -mno-ginv turns off this option." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Generate code for the Loongson MultiMedia extensions Instructions (MMI) Application Specific Extension. This tells the assembler to accept MMI instructions. -mno-loongson-mmi turns off this option." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Generate code for the Loongson Content Address Memory (CAM) instructions. This tells the assembler to accept Loongson CAM instructions. -mno-loongson-cam turns off this option." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Generate code for the Loongson EXTensions (EXT) instructions. This tells the assembler to accept Loongson EXT instructions. -mno-loongson-ext turns off this option." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Generate code for the Loongson EXTensions R2 (EXT2) instructions. This option implies -mloongson-ext. This tells the assembler to accept Loongson EXT2 instructions. -mno-loongson-ext2 turns off this option." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Only use 32-bit instruction encodings when generating code for the microMIPS processor. This option inhibits the use of any 16-bit instructions. This is equivalent to putting \".set insn32\" at the start of the assembly file. -mno-insn32 turns off this option. This is equivalent to putting \".set noinsn32\" at the start of the assembly file. By default -mno-insn32 is selected, allowing all instructions to be used." }, { "flag": "", "long": "--construct-floats", "arg": null, "description": "" }, { "flag": "", "long": "--no-construct-floats", "arg": null, "description": "The --no-construct-floats option disables the construction of double width floating point constants by loading the two halves of the value into the two single width floating point registers that make up the double width register. By default --construct-floats is selected, allowing construction of these floating point constants." }, { "flag": "", "long": "--relax-branch", "arg": null, "description": "" }, { "flag": "", "long": "--no-relax-branch", "arg": null, "description": "The --relax-branch option enables the relaxation of out-of-range branches. By default --no-relax-branch is selected, causing any out-of-range branches to produce an error." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Ignore branch checks for invalid transitions between ISA modes. The semantics of branches does not provide for an ISA mode switch, so in most cases the ISA mode a branch has been encoded for has to be the same as the ISA mode of the branch's target label. Therefore GAS has checks implemented that verify in branch assembly that the two ISA modes match. -mignore-branch-isa disables these checks. By default -mno-ignore-branch-isa is selected, causing any invalid branch requiring a transition between ISA modes to produce an error." }, { "flag": "", "long": null, "arg": null, "description": "Select between the IEEE 754-2008 (-mnan=2008) or the legacy (-mnan=legacy) NaN encoding format. The latter is the default. --emulation=name This option was formerly used to switch between ELF and ECOFF output on targets like IRIX 5 that supported both. MIPS ECOFF support was removed in GAS 2.24, so the option now serves little purpose. It is retained for backwards compatibility. The available configuration names are: mipself, mipslelf and mipsbelf. Choosing mipself now has no effect, since the output is always ELF. mipslelf and mipsbelf select little- and big-endian output respectively, but -EL and -EB are now the preferred options instead." }, { "flag": "", "long": null, "arg": null, "description": "as ignores this option. It is accepted for compatibility with the native tools." }, { "flag": "", "long": "--trap", "arg": null, "description": "" }, { "flag": "", "long": "--no-trap", "arg": null, "description": "" }, { "flag": "", "long": "--break", "arg": null, "description": "" }, { "flag": "", "long": "--no-break", "arg": null, "description": "Control how to deal with multiplication overflow and division by zero. --trap or --no-break (which are synonyms) take a trap exception (and only work for Instruction Set Architecture level 2 and higher); --break or --no-trap (also synonyms, and the default) take a break exception." }, { "flag": "-n", "long": null, "arg": null, "description": "instruction from a macro. The following options are available when as is configured for a LoongArch processor." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Generate position-independent code" }, { "flag": "", "long": null, "arg": null, "description": "Don't generate position-independent code (default) The following options are available when as is configured for a Meta processor. \"-mcpu=metac11\" Generate code for Meta 1.1. \"-mcpu=metac12\" Generate code for Meta 1.2. \"-mcpu=metac21\" Generate code for Meta 2.1. \"-mfpu=metac21\" Allow code to use FPU hardware of Meta 2.1. See the info pages for documentation of the MMIX-specific options. The following options are available when as is configured for a NDS32 processor. \"-O1\" Optimize for performance. \"-Os\" Optimize for space. \"-EL\" Produce little endian data output. \"-EB\" Produce little endian data output. \"-mpic\" Generate PIC. \"-mno-fp-as-gp-relax\" Suppress fp-as-gp relaxation for this file. \"-mb2bb-relax\" Back-to-back branch optimization. \"-mno-all-relax\" Suppress all relaxation for this file. \"-march=\" Assemble for architecture which could be v3, v3j, v3m, v3f, v3s, v2, v2j, v2f, v2s. \"-mbaseline=\" Assemble for baseline which could be v2, v3, v3m. \"-mfpu-freg=FREG\" Specify a FPU configuration. \"0 8 SP / 4 DP registers\" \"1 16 SP / 8 DP registers\" \"2 32 SP / 16 DP registers\" \"3 32 SP / 32 DP registers\" \"-mabi=abi\" Specify a abi version could be v1, v2, v2fp, v2fpp. \"-m[no-]mac\" Enable/Disable Multiply instructions support. \"-m[no-]div\" Enable/Disable Divide instructions support. \"-m[no-]16bit-ext\" Enable/Disable 16-bit extension \"-m[no-]dx-regs\" Enable/Disable d0/d1 registers \"-m[no-]perf-ext\" Enable/Disable Performance extension \"-m[no-]perf2-ext\" Enable/Disable Performance extension 2 \"-m[no-]string-ext\" Enable/Disable String extension \"-m[no-]reduced-regs\" Enable/Disable Reduced Register configuration (GPR16) option \"-m[no-]audio-isa-ext\" Enable/Disable AUDIO ISA extension \"-m[no-]fpu-sp-ext\" Enable/Disable FPU SP extension \"-m[no-]fpu-dp-ext\" Enable/Disable FPU DP extension \"-m[no-]fpu-fma\" Enable/Disable FPU fused-multiply-add instructions \"-mall-ext\" Turn on all extensions and instructions support The following options are available when as is configured for a PowerPC processor." }, { "flag": "", "long": null, "arg": null, "description": "Generate ELF32 or XCOFF32." }, { "flag": "", "long": null, "arg": null, "description": "Generate ELF64 or XCOFF64." }, { "flag": "-K", "long": null, "arg": "PIC", "description": "Set EFPPCRELOCATABLELIB in ELF flags." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for POWER/2 (RIOS2)." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for POWER (RIOS1)" }, { "flag": "", "long": null, "arg": null, "description": "Generate code for PowerPC 601." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for PowerPC 603/604." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for PowerPC 403/405." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for PowerPC 440. BookE and some 405 instructions." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for PowerPC 464." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for PowerPC 476." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for PowerPC 7400/7410/7450/7455." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for PowerPC 750CL/Gekko/Broadway." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for PowerPC 821/850/860." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for PowerPC 620/625/630." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for Motorola e500 core complex." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for Freescale e500mc core complex." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for Freescale e500mc64 core complex." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for Freescale e5500 core complex." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for Freescale e6500 core complex." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for Motorola SPE instructions." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for Freescale SPE2 instructions." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for AppliedMicro Titan core complex." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for PowerPC 64, including bridge insns." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for 32-bit BookE." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for A2 architecture." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for PowerPC e300 family." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for processors with AltiVec instructions." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for Freescale PowerPC VLE instructions." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for processors with Vector-Scalar (VSX) instructions." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for processors with Hardware Transactional Memory instructions." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for Power4 architecture." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for Power5 architecture." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for Power6 architecture." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for Power7 architecture." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for Power8 architecture." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for Power9 architecture." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for Power10 architecture." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Generate code for Cell Broadband Engine architecture." }, { "flag": "", "long": null, "arg": null, "description": "Generate code Power/PowerPC common instructions." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for any architecture (PWR/PWRX/PPC)." }, { "flag": "", "long": null, "arg": null, "description": "Allow symbolic names for registers." }, { "flag": "", "long": null, "arg": null, "description": "Do not allow symbolic names for registers." }, { "flag": "", "long": null, "arg": null, "description": "Support for GCC's -mrelocatable option." }, { "flag": "", "long": null, "arg": null, "description": "Support for GCC's -mrelocatable-lib option." }, { "flag": "", "long": null, "arg": null, "description": "Set PPCEMB bit in ELF flags." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for a little endian machine." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for a big endian machine." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for Solaris." }, { "flag": "", "long": null, "arg": null, "description": "Do not generate code for Solaris." }, { "flag": "", "long": null, "arg": null, "description": "If an alignment directive inserts more than count nops, put a branch at the beginning to skip execution of the nops. The following options are available when as is configured for a RISC-V processor." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Generate position-independent code" }, { "flag": "", "long": null, "arg": null, "description": "Don't generate position-independent code (default)" }, { "flag": "", "long": null, "arg": null, "description": "Select the base isa, as specified by ISA. For example -march=rv32ima. If this option and the architecture attributes aren't set, then assembler will check the default configure setting --with-arch=ISA." }, { "flag": "", "long": null, "arg": null, "description": "Select the default isa spec version. If the version of ISA isn't set by -march, then assembler helps to set the version according to the default chosen spec. If this option isn't set, then assembler will check the default configure setting --with-isa-spec=ISAspec." }, { "flag": "", "long": null, "arg": null, "description": "Select the privileged spec version. We can decide whether the CSR is valid or not according to the chosen spec. If this option and the privilege attributes aren't set, then assembler will check the default configure setting --with-priv-spec=PRIVspec." }, { "flag": "", "long": null, "arg": null, "description": "Selects the ABI, which is either \"ilp32\" or \"lp64\", optionally followed by \"f\", \"d\", or \"q\" to indicate single-precision, double-precision, or quad-precision floating-point calling convention, or none to indicate the soft-float calling convention. Also, \"ilp32\" can optionally be followed by \"e\" to indicate the RVE ABI, which is always soft-float." }, { "flag": "", "long": null, "arg": null, "description": "Take advantage of linker relaxations to reduce the number of instructions required to materialize symbol addresses. (default)" }, { "flag": "", "long": null, "arg": null, "description": "Don't do linker relaxations." }, { "flag": "", "long": null, "arg": null, "description": "Generate the default contents for the riscv elf attribute section if the .attribute directives are not set. This section is used to record the information that a linker or runtime loader needs to check compatibility. This information includes ISA string, stack alignment requirement, unaligned memory accesses, and the major, minor and revision version of privileged specification." }, { "flag": "", "long": null, "arg": null, "description": "Don't generate the default riscv elf attribute section if the .attribute directives are not set." }, { "flag": "", "long": null, "arg": null, "description": "Enable the CSR checking for the ISA-dependent CRS and the read-only CSR. The ISA- dependent CSR are only valid when the specific ISA is set. The read-only CSR can not be written by the CSR instructions." }, { "flag": "", "long": null, "arg": null, "description": "Don't do CSR checking." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for a little endian machine." }, { "flag": "", "long": null, "arg": null, "description": "Generate code for a big endian machine. See the info pages for documentation of the RX-specific options. The following options are available when as is configured for the s390 processor family." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Select the word size, either 31/32 bits or 64 bits." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Select the architecture mode, either the Enterprise System Architecture (esa) or the z/Architecture mode (zarch)." }, { "flag": "", "long": null, "arg": null, "description": "Specify which s390 processor variant is the target, g5 (or arch3), g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec (or arch7), z10 (or arch8), z196 (or arch9), zEC12 (or arch10), z13 (or arch11), z14 (or arch12), z15 (or arch13), or z16 (or arch14)." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Allow or disallow symbolic names for registers." }, { "flag": "", "long": null, "arg": null, "description": "Warn whenever the operand for a base or index register has been specified but evaluates to zero. The following options are available when as is configured for a TMS320C6000 processor." }, { "flag": "", "long": null, "arg": null, "description": "Enable (only) instructions from architecture arch. By default, all instructions are permitted. The following values of arch are accepted: \"c62x\", \"c64x\", \"c64x+\", \"c67x\", \"c67x+\", \"c674x\"." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "The -mdsbt option causes the assembler to generate the \"TagABIDSBT\" attribute with a value of 1, indicating that the code is using DSBT addressing. The -mno-dsbt option, the default, causes the tag to have a value of 0, indicating that the code does not use DSBT addressing. The linker will emit a warning if objects of different type (DSBT and non- DSBT) are linked together." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "The -mpid= option causes the assembler to generate the \"TagABIPID\" attribute with a value indicating the form of data addressing used by the code. -mpid=no, the default, indicates position-dependent data addressing, -mpid=near indicates position-independent addressing with GOT accesses using near DP addressing, and -mpid=far indicates position- independent addressing with GOT accesses using far DP addressing. The linker will emit a warning if objects built with different settings of this option are linked together." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "The -mpic option causes the assembler to generate the \"TagABIPIC\" attribute with a value of 1, indicating that the code is using position-independent code addressing, The \"-mno-pic\" option, the default, causes the tag to have a value of 0, indicating position- dependent code addressing. The linker will emit a warning if objects of different type (position-dependent and position-independent) are linked together." }, { "flag": "", "long": null, "arg": null, "description": "" }, { "flag": "", "long": null, "arg": null, "description": "Generate code for the specified endianness. The default is little-endian. The following options are available when as is configured for a TILE-Gx processor." }, { "flag": "", "long": null, "arg": null, "description": "Select the word size, either 32 bits or 64 bits." }, { "flag": "", "long": null, "arg": null, "description": "Select the endianness, either big-endian (-EB) or little-endian (-EL). The following option is available when as is configured for a Visium processor." }, { "flag": "", "long": null, "arg": null, "description": "This option specifies the target architecture. If an attempt is made to assemble an instruction that will not execute on the target architecture, the assembler will issue an error message. The following names are recognized: \"mcm24\" \"mcm\" \"gr5\" \"gr6\" The following options are available when as is configured for an Xtensa processor." }, { "flag": "", "long": "--no-text-section-literals", "arg": null, "description": "Control the treatment of literal pools. The default is --no-text-section-literals, which places literals in separate sections in the output file. This allows the literal pool to be placed in a data RAM/ROM. With --text-section-literals, the literals are interspersed in the text section in order to keep them as close as possible to their references. This may be necessary for large assembly files, where the literals would otherwise be out of range of the \"L32R\" instructions in the text section. Literals are grouped into pools following \".literalposition\" directives or preceding \"ENTRY\" instructions. These options only affect literals referenced via PC-relative \"L32R\" instructions; literals for absolute mode \"L32R\" instructions are handled separately." }, { "flag": "", "long": "--no-auto-litpools", "arg": null, "description": "Control the treatment of literal pools. The default is --no-auto-litpools, which in the absence of --text-section-literals places literals in separate sections in the output file. This allows the literal pool to be placed in a data RAM/ROM. With --auto-litpools, the literals are interspersed in the text section in order to keep them as close as possible to their references, explicit \".literalposition\" directives are not required. This may be necessary for very large functions, where single literal pool at the beginning of the function may not be reachable by \"L32R\" instructions at the end. These options only affect literals referenced via PC-relative \"L32R\" instructions; literals for absolute mode \"L32R\" instructions are handled separately. When used together with --text-section-literals, --auto-litpools takes precedence." }, { "flag": "", "long": "--no-absolute-literals", "arg": null, "description": "Indicate to the assembler whether \"L32R\" instructions use absolute or PC-relative addressing. If the processor includes the absolute addressing option, the default is to use absolute \"L32R\" relocations. Otherwise, only the PC-relative \"L32R\" relocations can be used." }, { "flag": "", "long": "--no-target-align", "arg": null, "description": "Enable or disable automatic alignment to reduce branch penalties at some expense in code size. This optimization is enabled by default. Note that the assembler will always align instructions like \"LOOP\" that have fixed alignment requirements." }, { "flag": "", "long": "--no-longcalls", "arg": null, "description": "Enable or disable transformation of call instructions to allow calls across a greater range of addresses. This option should be used when call targets can potentially be out of range. It may degrade both code size and performance, but the linker can generally optimize away the unnecessary overhead when a call ends up within range. The default is --no-longcalls." }, { "flag": "", "long": "--no-transform", "arg": null, "description": "Enable or disable all assembler transformations of Xtensa instructions, including both relaxation and optimization. The default is --transform; --no-transform should only be used in the rare cases when the instructions must be exactly as specified in the assembly source. Using --no-transform causes out of range instruction operands to be errors. --rename-section oldname=newname Rename the oldname section to newname. This option can be used multiple times to rename multiple sections." }, { "flag": "", "long": "--no-trampolines", "arg": null, "description": "Enable or disable transformation of jump instructions to allow jumps across a greater range of addresses. This option should be used when jump targets can potentially be out of range. In the absence of such jumps this option does not affect code size or performance. The default is --trampolines." }, { "flag": "", "long": "--abi-call0", "arg": null, "description": "Choose ABI tag written to the \".xtensa.info\" section. ABI tag indicates ABI of the assembly code. A warning is issued by the linker on an attempt to link object files with inconsistent ABI tags. Default ABI is chosen by the Xtensa core configuration. The following options are available when as is configured for an Z80 processor. @chapter Z80 Dependent Features" }, { "flag": "", "long": null, "arg": null, "description": "This option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following processor names are recognized: \"z80\", \"z180\", \"ez80\", \"gbz80\", \"z80n\", \"r800\". In addition to the basic instruction set, the assembler can be told to accept some extention mnemonics. For example, \"-march=z180+sli+infc\" extends z180 with SLI instructions and IN F,(C). The following extentions are currently supported: \"full\" (all known instructions), \"adl\" (ADL CPU mode by default, eZ80 only), \"sli\" (instruction known as SLI, SLL or SL1), \"xyhl\" (instructions with halves of index registers: IXL, IXH, IYL, IYH), \"xdcb\" (instructions like RotOp (II+d),R and BitOp n,(II+d),R), \"infc\" (instruction IN F,(C) or IN (C)), \"outc0\" (instruction OUT (C),0). Note that rather than extending a basic instruction set, the extention mnemonics starting with \"-\" revoke the respective functionality: \"-march=z80-full+xyhl\" first removes all default extentions and adds support for index registers halves only. If this option is not specified then \"-march=z80+xyhl+infc\" is assumed." }, { "flag": "", "long": null, "arg": null, "description": "Mark all labels with specified prefix as local. But such label can be marked global explicitly in the code. This option do not change default local label prefix \".L\", it is just adds new one." }, { "flag": "", "long": null, "arg": null, "description": "Accept colonless labels. All symbols at line begin are treated as labels." }, { "flag": "", "long": null, "arg": null, "description": "Accept assembler code produced by SDCC." }, { "flag": "", "long": null, "arg": null, "description": "Single precision floating point numbers format. Default: ieee754 (32 bit)." }, { "flag": "", "long": null, "arg": null, "description": "Double precision floating point numbers format. Default: ieee754 (64 bit)." } ], "examples": [], "see_also": [ { "name": "gcc", "section": "1", "url": "https://www.chedong.com/phpMan.php/man/gcc/1/json" }, { "name": "ld", "section": "1", "url": "https://www.chedong.com/phpMan.php/man/ld/1/json" } ], "tldr": { "source": "official", "description": "Portable GNU assembler.", "examples": [ { "description": "Assemble a file, writing the output to `a.out`", "command": "as {{path/to/file.s}}" }, { "description": "Assemble the output to a given file", "command": "as {{path/to/file.s}} -o {{path/to/output_file.o}}" }, { "description": "Generate output faster by skipping whitespace and comment preprocessing. (Should only be used for trusted compilers)", "command": "as -f {{path/to/file.s}}" }, { "description": "Include a given path to the list of directories to search for files specified in `.include` directives", "command": "as -I {{path/to/directory}} {{path/to/file.s}}" } ] } }